Abstract
The increased demands for quality, like high throughput, low-latency, wide coverage, energy consumption, cost and reliable connections in mobile services, multimedia, and data transmission impose the use of advance technical requirements for the next fifth-generation (5G) new radio (NR). One of the most crucial parts in the physical layer of the new generation is the error correction coding technique. Three schemes, namely “Turbo codes”, “low-density parity check (LDPC)”, and “polar codes” are potentially considered as the candidate codes for both data and control channels. The competition is evaluated in terms of error correction capability, computational complexity, and flexibility. The parallelism, flexibility, and high processing speed of “field-programmable gate array (FPGA)” make it preferable in prototyping and implementation of different codes. In this paper, design, implementation, experimental verification, and validation of the quasi-cyclic LDPC encoder and decoder are proposed on the AWGN channel using Kintex-7 FPGA. Codewords are constructed and simulated for different length and rates. The performance and architectural complexity in terms of the throughput and silicon area are presented based on Vivado high-level synthesis (HLS). The paper also studies the effect of applying scaling factors to alleviate the overestimation of the “extrinsic information” that exchanges during the iterative decoding process.
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Tamkeen, S.A., Hamad, A.A. (2021). FPGA Implementation of Scaled “Quasi-Cyclic LDPC” Decoder Using High-Level Synthesis. In: Peng, SL., Hao, RX., Pal, S. (eds) Proceedings of First International Conference on Mathematical Modeling and Computational Science. Advances in Intelligent Systems and Computing, vol 1292. Springer, Singapore. https://doi.org/10.1007/978-981-33-4389-4_14
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DOI: https://doi.org/10.1007/978-981-33-4389-4_14
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