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PAM: an efficient power-aware multilevel cache policy to reduce energy consumption of storage systems

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Abstract

Energy consumption is one of the most significant aspects of large-scale storage systems where multilevel caches are widely used. In a typical hierarchical storage structure, upper-level storage serves as a cache for the lower level, forming a distributed multilevel cache system. In the past two decades, several classic LRU-based multilevel cache policies have been proposed to improve the overall I/O performance of storage systems. However, few power-aware multilevel cache policies focus on the storage devices in the bottom level, which consume more than 27% of the energy of the whole system [1].

To address this problem, we propose a novel power-aware multilevel cache (PAM) policy that can reduce the energy consumption of high-performance and I/O bandwidth storage devices. In our PAM policy, an appropriate number of cold dirty blocks in the upper level cache are identified and selected to flush directly to the storage devices, providing high probability extension of the lifetime of disks in standby mode. To demonstrate the effectiveness of our proposed policy, we conduct several simulations with real-world traces. Compared to existing popular cache schemes such as PA-LRU, PB-LRU, and Demote, PAM reduces power consumption by up to 15% under different I/O workloads, and improves energy efficiency by up to 50.5%.

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Acknowledgements

We thank anonymous reviewers for their insightful comments. This work was partially sponsored by the National 863 Program of China (No. 2015AA015302), National 973 Program of China (No. 2015CB352403), and the National Natural Science Foundation of China (NSFC) (Grant Nos. 61572323 and 61628208).

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Authors and Affiliations

  1. Shanghai Key Laboratory of Scalable Computing and Systems, Department of Computer Science & Engineering, Shanghai Jiao Tong University, Shanghai, 200240, China

    Xiaodong Meng, Chentao Wu, Minyi Guo, Long Zheng & Jingyu Zhang

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  1. Xiaodong Meng
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Correspondence to Xiaodong Meng.

Additional information

Xiaodong Meng is a PhD student of computer science in Shanghai Jiao Tong University, China. He received his Bachelor’s degree in electronic information science and technology from Wuhan University, China in 2007 and Master’s degree in information technology from Monash University, Australia in 2010. His main interest is in parallel and distributed computing, social graph processing and storage systems.

Chentao Wu received the PhD degree in electrical and computer engineering from Virginia Commonwealth University, Virginia, USA in 2012. He received the ME degree in software engineering in 2006 and the BE degree in computer science and technology in 2004 from Huazhong University of Science and Technology, China. He is currently an assistant professor in the Department of Computer Science and Engineering at Shanghai Jiao Tong University, China. His research interests include computer architecture and data storage systems.

Minyi Guo received the BS and ME degrees in computer science from Nanjing University, China in 1982 and 1986, respectively. He received the PhD degree in information science from University of Tsukuba, Japan in 1998. From 1998 to 2000, Dr. Guo had been a research associate of NEC Soft, Ltd., Japan. He was a full professor at The University of Aizu, Japan and is Head of Department of Computer Science and Engineering at Shanghai Jiao Tong University, China. He is an IEEE senior member and has published more than 150 papers in well-known conferences and journals. His main interests include automatic parallelization and data-parallel languages, bioinformatics, compiler optimization, high performance computing, and pervasive computing.

Long Zheng received the BS degree in computer science and technology from Huazhong University of Science and Technology (HUST), China in 2006, MS degree in computer science and engineering from the University of Aizu, Aizu-Wakamatsu, Japan in 2009 and MS degree in computer science and technology from HUST in 2010. He is now a PhD student at School of Computer Science and Engineering, the University of Aizu and also a PhD student at School of Computer Science and Technology, HUST.He is currently a visiting scholar with Embedded and Pervasive Computing Center (EPCC) at Shanghai Jiaotong University, China from October 2010 to March 2011. His research interests include chip multiprocessor, parallel and distributed processing, and pervasive computing.

Jingyu Zhang received the BE degree in communication engineering from Hunan Normal University, China in 2008, and the ME degree in computer science from Chongqing Jiaotong University, China in 2010. He is currently a PhD candidate at the Department of Computer Science and Engineering, Shanghai Jiao Tong University, China. His research interests include mobile networks, energy optimization, and computer architecture.

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Meng, X., Wu, C., Guo, M. et al. PAM: an efficient power-aware multilevel cache policy to reduce energy consumption of storage systems. Front. Comput. Sci. 13, 850–863 (2019). https://doi.org/10.1007/s11704-017-6500-3

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