Abstract
The multiplication of computing cores in modern processor units permits revisiting the design of classical algorithms to improve computational performance in complex application domains. Artificial Intelligence planning is one of those applications where large search spaces require intelligent and more exhaustive search control. In this paper, parallel planning algorithms, derived from best-first search, are proposed for shared memory architectures. The parallel algorithms, based on the asynchronous work pool paradigm, maintain good thread occupancy in multi-core CPUs. All algorithms use one ordered global list of states stored in shared memory from where they select nodes for expansion. A parallel best-first search algorithm that develops new states with depth equal to one is proposed first. Then, we propose an extension of this parallel algorithm that features a diversification strategy in order to escape local minima. We study and analyse a set of computational experiments for problems that come from the International Planning Competition and real-world industry applications. The empirical evaluation shows that the parallel algorithms solve most of the domains efficiently without incurring higher solutions costs. In those problems with partial results, we highlight the potential shortcomings of the proposed approaches for promising future directions.
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For this study, we have used benchmark planning problems from the International Planning Competition (IPC), which are available in the public domain. The source of the dataset is cited in the paper. The problems from real-world applications are available upon request.
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The code is available on request.
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Acknowledgements
We thank SUPE reviewers for many constructive comments of the proposed work.
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Part of this study has been made possible via a funding of project BigGraphs of LABEX CIMI 2020, Toulouse and UANL PAICYT Grant IT1838-21.
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El Baz, D., Fakih, B., Sanchez Nigenda, R. et al. Parallel best-first search algorithms for planning problems on multi-core processors. J Supercomput 78, 3122–3151 (2022). https://doi.org/10.1007/s11227-021-03986-z
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DOI: https://doi.org/10.1007/s11227-021-03986-z