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Dual-mode inter-router communication channel for deflection-routed networks-on-chip

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Abstract

Deflection routing, characterized by routing simplicity and minimal in-router buffer resources, has recently emerged as a promising approach for improving power and area efficiency of on-chip networks. With this routing strategy, packet contentions in routers are resolved by intentionally misrouting some of packets along unwanted directions instead of storing them. However, at higher network loads, when the contentions are more frequent, packets take longer paths on average to their destinations, and thus increase the energy consumption, delay, and reduce the throughput in the network. To address this problem, we enhance the inter-router communication channels with a lightweight link-control mechanism that prevents unnecessary network hops by forcing deflected packets, when possible, to loop back to their current routers instead of being misrouted. The effect of the packet loop-backing is similar to that of storing deflected packet into a small central in-router buffer, but is accomplished with lower implementation cost (i.e. there is no need for additional buffer memory) and without any modification to the underlying router microarchitecture. Evaluations on synthetic traffic patterns show that the proposed misrouting suppression mechanism yields an improvement of 11.8–14.5 % in network saturation throughput when coupled with the conventional bufferless and buffered deflection-based routers.

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References

  1. Owens JD, Dally WJ, Ho R, Jayasimha DN, Keckler SW, Peh LS (2007) Research challenges for on-chip interconnection networks. IEEE Micro 27(5):96–108. doi:10.1109/MM.2007.4378787

    Article  Google Scholar 

  2. Borkar S (2010) Future of interconnect fabric: a contrarian view. In: Proceidings of 12th ACM/IEEE international workshop on system level interconnect prediction. ACM, New York, pp 1–2. doi:10.1145/1811100.1811101

  3. Arteris (2005) A comparison of network-on-chip and busses. http://www.arteris.com/nocwhitepaper.pdf. Accessed 27 Oct 2014

  4. Gebali F, Elmiligi H, El-Kharashi MW (2009) Networks-on-chips:theory and practice. Taylor & Francis Group LLC, Washington, DC

    Google Scholar 

  5. Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th conference on design automation. ACM, New York, pp 684–689. doi:10.1109/DAC.2001.156225

  6. Dally WJ, James W, Towles B (2003) Principles and practices of interconnection networks. Morgan Kaufmann Publishers Inc., San Francisco

    Google Scholar 

  7. Ni LM (1993) A survey of wormhole routing techniques in direct networks. Computer 26(2):62–76. doi:10.1109/2.191995

    Article  Google Scholar 

  8. Dally WJ (1992) Virtual-channel flow control. IEEE Trans Parallel Distrib Syst 3(2):194–205. doi:10.1109/71.127260

    Article  Google Scholar 

  9. Kumar A, Kundu P, Singh A, Peh LS, Jha N (2007) A 4.6 Tbits/s 3.6 GHz single-cycle NOC router with a novel switch allocator in 65 nm CMOS. In: Proceedings of 25th international conference on computer design, ICCD, pp 63–70. doi:10.1109/ICCD.2007.4601881

  10. Moscibroda T, Mutlu O (2009) A case for bufferless routing in on-chip networks. In: Proceedings of the 36th annual international symposium on computer architecture. ACM, New York, pp 196–207. doi:10.1145/1555754.1555781

  11. Assad A, Mazhar A, Ahmad F et al (2014) A survey on energy-efficient meyhodologies and architectures of network-on-chip. Comput Electr Eng 40(8):333–347. doi:10.1016/j.compeleceng.2014.07.012

    Article  Google Scholar 

  12. Hayenga M (2009) SCARAB: a single cycle adaptive routing and bufferless network. In: Proceedings of the 42nd annual IEEE/ACM international symposium on microarchitecture (MICRO-42), pp 244–254. doi:10.1145/1669112.1669144

  13. Fallin C, Craik C, Mutlu O (2011) CHIPPER: a low-complexity bufferless deflection router. In: Proceedings of the 17th international symposium on high performance computer architecture (HPCA), 2011, pp 144–155. doi:10.1109/HPCA.2011.5749724

  14. Jose J, Nayak B, Kumar K, Muyam M (2013) DeBAR: deflection based adaptive router with minimal buffering. In: Proceedings of design, automation & test in Europe conference & exhibition (DATE), pp 1583–1588. doi:10.7873/DATE.2013.322

  15. Fallin C, Nazario G, Yu X, Chang K, Ausavarungnirun R, Mutlu O (2012) MinBD: minimally-buffered deflection routing for energy-efficient interconnect. In: Proceedings of the 6th IEEE/ACM international symposium on networks on chip, pp 1–10. doi:10.1109/NOCS.2012.8

  16. Jafri S, Hong Y, Thottethodi M, Vijaykumar T (2010) Adaptive flow control for robust performance and energy. In: Proceedings of the 43rd annual IEEE/ACM international symposium on microarchitecture, pp 433–444. doi:10.1109/MICRO.2010.48

  17. Yan J, Lai G, Lin X (2014) A novel distributed congestion control for bufferless network-on-chip. J Supercomput 68(2):849–866. doi:10.1007/s11227-013-1069-6

    Article  Google Scholar 

  18. Nychis GP, Fallin C, Moscibroda T, Mutlu O, Seshan S (2012) On-chip networks from a networking perspective: congestion and scalability in many-core interconnects. ACM SIGCOMM Comput Commun Rev 42(4):407–418. doi:10.1145/2342356.2342436

    Article  Google Scholar 

  19. Kohler A, Radetzki M (2009) Fault-tolerant architecture and deflection routing for degradable NoC switches. In: Proceedings of the 3rd IEEE international symposium on networks-on-chip, pp 22–31. doi:10.1109/NOCS.2009.5071441

  20. Feng C, Zhang M, Li J, Lu Z, Jantsch A (2011) A low-overhead fault-aware deflection routing algorithm for 3D network-on-chip. In: Proceedings of IEEE Computer Society annual symposium on VLSI (ISVLSI), pp 19–24. doi:10.1109/ISVLSI.2011.42

  21. Michelogiannakis G, Sanchez D, Dally WJ, Kozyrakis C (2010) Evaluating bufferless flow control for on-chip networks. In: Proceedings of the 4th ACM/IEEE international symposium on networks-on-chip, pp 9–16. doi:10.1109/NOCS.2010.10

  22. Zhang N, Huaxi G, Yang Y, Fan D (2014) QBNoC: QoS-aware bufferless NoC architecture. Microelectron J 45(6):751–758. doi:10.1016/j.mejo.2014.04.015

    Article  Google Scholar 

  23. Feng C, Li J, Lu Z, Jantsch A, Zhang M (2011) Evaluation of deflection routing on various NoC topologies. In: Proceedings of IEEE 9th international conference on ASIC (ASICON), pp 163–166. doi:10.1109/ASICON.2011.6157147

  24. Guz Z, Walter I, Bolotin E, Cidon I, Ginosar R, Kolodny A (2006) Efficient link capacity and QoS design for network-on-chip. In: Proceedings of design, automation and test in Europe, DATE ’06, pp 9–14. doi:10.1109/DATE.2006.243951

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Acknowledgments

This work was partially supported by the Serbian Ministry of Science and Technological Development Project No. TR-32009, TR-33035.

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Authors and Affiliations

  1. Faculty of Electronic Engineering, University of Nis, A. Medvedeva 14, 18000, Nis, Serbia

    Igor Z. Stojanovic, Milica D. Jovanovic & Goran Lj. Djordjevic

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  1. Igor Z. Stojanovic
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  2. Milica D. Jovanovic
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  3. Goran Lj. Djordjevic
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Correspondence to Igor Z. Stojanovic.

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Stojanovic, I.Z., Jovanovic, M.D. & Djordjevic, G.L. Dual-mode inter-router communication channel for deflection-routed networks-on-chip. J Supercomput 71, 2597–2613 (2015). https://doi.org/10.1007/s11227-015-1407-y

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