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Hybrid optimization algorithm applied for selective harmonic elimination in multilevel inverter with reduced switch topology

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Abstract

This paper presents, ant colony optimization based hybrid algorithm for selective harmonic elimination in single phase seven level multilevel inverter with reduced switches. For high power and high voltage applications, multilevel structure with selective harmonic elimination (SHE) modulation scheme is used. The output voltage of multilevel inverter contains fundamental component along with harmonics. SHE technique aims to solve non-linear transcendental equations maintaining the fundamental harmonic component to its desired value and to eliminate lower order odd harmonics. Many optimization algorithms have been implemented to solve this problem. But these algorithms are complicated and time consuming. The Newton–Raphson algorithm is also very convergent for solving these non-linear equations. The main disadvantage of this method is, it requires strong initial guess. To overcome these drawbacks, hybrid optimization algorithm is used in this paper. This algorithm is performed in two stages, during first stage ant colony optimization has been run and in second stage the solutions obtained from ACO is used as a initial guess for Newton–Raphson algorithm which confirms the exact converged solution. Thus the drawback of Newton’s method i.e. requirement of good initial guess is overcomed by proposed hybrid algorithm. The MATLAB/SlMULINK software is used for comprehensive simulation of seven-level inverter. Experimental results validate the simulated results.

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Authors and Affiliations

  1. Department of Electrical Engineering, Rajiv Gandhi College of Engineering and Research, Nagpur, India

    Sarika D. Patil

  2. Department of Electrical Engineering, Yeshwantrao Chavan College of Engineering, Nagpur, India

    Sumant G. Kadwane

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  1. Sarika D. Patil
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  2. Sumant G. Kadwane
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Correspondence to Sarika D. Patil.

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Patil, S.D., Kadwane, S.G. Hybrid optimization algorithm applied for selective harmonic elimination in multilevel inverter with reduced switch topology. Microsyst Technol 24, 3409–3415 (2018). https://doi.org/10.1007/s00542-018-3720-x

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  • DOI: https://doi.org/10.1007/s00542-018-3720-x

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