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A Low-Energy, Stable, Single-Bitline Accessed FinFET 9T-SRAM

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Abstract

SRAMs, the go-to choice for system-on-chips nowadays, suffer from high power consumption and unstable behavior in nanoscale CMOS technology. Consequently, we observe the emergence of troublesome short-channel effects (SCEs), necessitating the utilization of innovative nano-devices. Combining its attractive features, including reduced SCEs and leakage, the fin-shaped field-effect transistor (FinFET) shines as a skillful replacement for CMOS, skillfully tackling those injurious problems. This paper presents a near-threshold single-bitline 9T (SB9T) SRAM cell, with a primary focus on enhancing stability and energy efficiency. The SB9T SRAM cell integrates a read-assist scheme and a feedback-cutting technique to enhance read stability and writability. By conducting simulations utilizing a 7-nm FinFET technology and operating at a voltage of 0.5 V, the SB9T SRAM cell demonstrates remarkable performance advantages when compared to existing designs. Specifically, in comparison to the conventional 6T cell, the SB9T SRAM cell achieves an improvement of 1.86 × in read stability and 2.41 × in writability. Additionally, the SB9T SRAM cell minimizes power dissipation from leakage by at least 8.73% and enhances write energy efficiency by a minimum of 4.84%. It should be noted that although the SB9T SRAM cell consumes 1.03 × more read energy than the conventional 8T cell, it still surpasses alternative designs by reducing read energy consumption by at least 4.86%.

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References

  1. E. Abbasian, A highly stable low-energy 10T SRAM for near-threshold operation. IEEE Trans. Circuits Syst. I Regul. Pap.Circuits Syst. I Regul. Pap. 69(12), 5195–5205 (2022)

    Article  Google Scholar 

  2. E. Abbasian, M. Gholipour, S. Birla, A single-bitline 9T SRAM for low-power near-threshold operation in FinFET technology. Arab. J. Sci. Eng. 47, 14543–14559 (2022)

    Article  Google Scholar 

  3. E. Abbasian, F. Izadinasab, M. Gholipour, A reliable low standby power 10T SRAM cell with expanded static noise margins. IEEE Trans. Circuits Syst. I Regul. Pap.Circuits Syst. I Regul. Pap. 69(4), 1606–1616 (2022)

    Article  Google Scholar 

  4. E. Abbasian, S. Sofimowloodi, Energy-efficient single-ended read/write 10T near-threshold SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5), 2037–2047 (2023)

    Article  Google Scholar 

  5. S. Ahmad, M.K. Gupta, N. Alam, M. Hasan, Single-ended Schmitt-trigger-based robust low-power SRAM cell. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24, 2634–2642 (2016)

    Article  Google Scholar 

  6. M. Ansari, H. Afzali-Kusha, B. Ebrahimi, Z. Navabi, A. Afzali-Kusha, M. Pedram, A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. Integration 50, 91–106 (2015)

    Article  Google Scholar 

  7. M.-H. Chang, Y.-T. Chiu, W. Hwang, Design and Iso-area Vmin analysis of 9T subthreshold SRAM with bit-interleaving scheme in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 59, 429–433 (2012)

    Google Scholar 

  8. I.J. Chang, J.-J. Kim, S.P. Park, K. Roy, A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS. IEEE J. Solid-State Circuits 44, 650–658 (2009)

    Article  Google Scholar 

  9. L. Chang, R.K. Montoye, Y. Nakamura, K.A. Batson, R.J. Eickemeyer, R.H. Dennard et al., An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches. IEEE J. Solid-State Circuits 43, 956–963 (2008)

    Article  Google Scholar 

  10. K. Cho, J. Park, T.W. Oh, S.-O. Jung, One-sided schmitt-trigger-based 9T SRAM cell for near-threshold operation. IEEE Trans. Circuits Syst. I Regul. Pap. 67, 1551–1561 (2020)

    Article  Google Scholar 

  11. L.T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, G. Yeric, ASAP7: A 7-nm finFET predictive process design kit. Microelectron. J. 53, 105–115 (2016)

    Article  Google Scholar 

  12. K. Endo, Y. Ishikawa, Y. Liu, T. Matsukawa, K. Sakamoto, J. Tsukada et al., Variability analysis of TiN metal-gate FinFETs. IEEE Electron. Dev. Lett. 31, 546–548 (2010)

    Article  Google Scholar 

  13. S.S. Ensan, M.H. Moaiyeri, S. Hessabi, A robust and low-power near-threshold SRAM in 10-nm FinFET technology. Analog Integr. Circ. Signal Process. 94, 497–506 (2018)

    Article  Google Scholar 

  14. S.S. Ensan, M.H. Moaiyeri, M. Moghaddam, S. Hessabi, A low-power single-ended SRAM in FinFET technology. AEU-Int. J. Electron. Commun. 99, 361–368 (2019)

    Article  Google Scholar 

  15. S. Gupta, K. Gupta, B.H. Calhoun, N. Pandey, Low-power near-threshold 10T SRAM bit cells with enhanced data-independent read port leakage for array augmentation in 32-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66, 978–988 (2018)

    Article  Google Scholar 

  16. Y. He, J. Zhang, X. Wu, X. Si, S. Zhen, B. Zhang, A half-select disturb-free 11T SRAM cell with built-in write/read-assist scheme for ultralow-voltage operations. IEEE Trans. Very Large Scale Integr. VLSI Syst. 27, 2344–2353 (2019)

    Article  Google Scholar 

  17. D. Ingerly, A. Agrawal, R. Ascazubi, A. Blattner, M. Buehler, V. Chikarmane, et al., Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing, Proc. 2012 IEEE International Interconnect Technology Conference, 1-3. (2012).

  18. M.R. Jan, C. Anantha, N. Borivoje, Digital Integrated Circuits: A Design Perspective (Prentice Hall Upper Saddle River, 2003)

    Google Scholar 

  19. J.P. Kulkarni, K. Kim, K. Roy, A 160 mV robust Schmitt trigger based subthreshold SRAM. IEEE J. Solid-State Circuits 42, 2303–2313 (2007)

    Article  Google Scholar 

  20. M. Limachia, R. Thakker, N. Kothari, A near-threshold 10t differential sram cell with high read and write margins for tri-gated finfet technology. Integration 61, 125–137 (2018)

    Article  Google Scholar 

  21. D. D. Lu, C.-H. Lin, S. Yao, W. Xiong, F. Bauer, C. R. Cleavelin, et al., Design of FinFET SRAM cells using a statistical compact model, Proc. 2009 International Conference on Simulation of Semiconductor Processes and Devices 1–4. (2009).

  22. J.S. Oh, J. Park, K. Cho, T.W. Oh, S.-O. Jung, Differential read/write 7T SRAM with bit-interleaved structure for near-threshold operation. IEEE Access 9, 64105–64115 (2021)

    Article  Google Scholar 

  23. G. Pasandi, S.M. Fakhraie, A 256-kb 9T near-threshold SRAM with 1k cells per bitline and enhanced write and read operations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23, 2438–2446 (2014)

    Article  Google Scholar 

  24. S. Ruhil, V. Khanna, U. Dutta, N.K. Shukla, A 7T high stable and low power SRAM cell design using QG-SNS FinFET. AEU-Int. J. Electron. Commun. 162, 154704 (2023)

    Article  Google Scholar 

  25. A. Sachdeva, D. Kumar, E. Abbasian, A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time. AEU-Int. J. Electron. Commun. 162, 154565 (2023)

    Article  Google Scholar 

  26. S.M. Salahuddin, M. Chan, Eight-FinFET fully differential SRAM cell with enhanced read and write voltage margins. IEEE Trans. Electron Devices 62, 2014–2021 (2015)

    Article  Google Scholar 

  27. S. Salahuddin, H. Jiao, and V. Kursun, A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability, Proc. International symposium on quality electronic design (ISQED), 353–358. (2013).

  28. L. Soni, N. Pandey, A novel CNTFET based Schmitt-Trigger read decoupled 12T SRAM cell with high speed, low power, and high Ion/Ioff ratio. AEU-Int. J. Electron. Commun. 167, 154669 (2023)

    Article  Google Scholar 

Download references

Acknowledgements

The authors wish to thank the reviewers for their insightful comments and suggestions, which have improved the quality of this paper.

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Correspondence to Erfan Abbasian.

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Abbasian, E., Nayeri, M. & Mani, E. A Low-Energy, Stable, Single-Bitline Accessed FinFET 9T-SRAM. Circuits Syst Signal Process 43, 5361–5376 (2024). https://doi.org/10.1007/s00034-024-02718-x

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