We optimize ternary logic circuits by minimizing the number of transistors with a modified Quine-McCluskey algorithm. Our proposed method has improved power- ...
We optimize ternary logic circuits by minimizing the number of transistors with a modified Quine-McCluskey algorithm. Our proposed method has improved power- ...
Jul 14, 2019 · To design the ternary logic gate using MTGB, we convert given truth table into the switching table which represents pullup and pull-down.
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm. Author, Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang. Journal, 2019 IEEE 49th International ...
A method of synthesizing a ternary logic based on a static gate design according to an example embodiment will be described. First, in a ternary logic synthesis ...
We can synthesize an optimized logic gate by proper placement of ternary logic devices in the VDD/GND path and half VDD path of the static logic gate. ...
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm ...
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Ternary logic synthesis with modified Quine-McCluskey algorithm. SY Lee, S Kim, S Kang. 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), ...
KR-102130980-B1 chemical patent summary.
The proposed algorithm results in circuits that have, on an average 79%, and up to 99% fewer transistors when compared with the most recent 3:1 multiplexer- ...