Abstract: A new programmable and automatically adjustable off-chip driver (OCD) and on-die terminator (ODT) for DDR3-SRAM interface are proposed, ...

The proposed programmable impedance controller (PIC) maintains constant resistance of the ODT within 3% variation, and supports DDR3-SRAM MODE. The new scheme ...

[7]. Kim N.S. et al (2003) 'Programmable and. Automatically Adjustable On-Die Terminator for. DDR3-SRAM interface', IEEE 2003 CUSTOM. INTEGRATED CIRCUITS ...

This paper deals with the high performance AXI protocol based improved DDR3 memory controller with improved memory bandwidth, which has backward compatibility ...

Kim, Nam-Seog et al., "Programmable and Automatically Adjustable On-Die Terminator for DDR3-SRAM Interface, "IEEE Customs Integrated Circuits Conference, Sep.

Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface ... Interface-Type Self-Rectifying Resistive Memory ...

A programmable impedance controller (PIC) creates the impedance ... Programmable and Automatically Adjustable On-Die Terminator for DDR3-SRAM Interface,...

A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory Interface · Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface · A 1.2 ...

実験的サービス公開サイトであるCiNii Labsを公開しました。 Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. 被 ...

The proposed driver design provides all the required output and termination impedances specified by both the DDR2 and DDR3 standards and occupies a small die ...