In this correspondence, the implementation of pipelined binary parallel counters with networks of latched quaternary threshold logic full adders is described ...
This paper describes the implementation of parallel counters with four-valued threshold logic in large-scale-integrated (LSI) circuit form and these ...
A four-valued logic full adder accepts two four-valued inputs and a binary carry input and produces a two-quaternary-digit, base-four, output word that is ...
A parallel counter is a combinational logic circuit that receives a set of binary count signals in parallel and determines the final count after some fixed ...
Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders. Parallel counters are multiple input circuits that count the number of ...
Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders pp. 400-403. A High Data-Rate Digital Output Correlator Design pp. 403-405.
K. Wayne Current: Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders. 400-403 BibTeX · K. Wayne Current: A High Data-Rate ...
Current, 1980: Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders IEEE Transactions on Computers C-29(5): 400-403 · Dorrigiv, M ...
Current, "Pipelined parallelcounters employing latched quaternary logic full adders," this issue, pp. 400-403. [6] D. R. Breuer, "Applications of low-level ...
In this correspondence, the implementation of pipelined binary parallel counters with networks of latched quaternary threshold logic full adders is described ...