In this paper, we propose a new optimization method for yield optimization under simultaneous leakage power and performance limits. The optimization approach ...

The “Yield” function is then used to compute the yield based on the timing and leakage power pdfs given a leakage power constraint P and a delay constraint D, ...

The optimization approach uses a novel leakage power and performance analysis that is statistical in nature and considers the correlation between leakage power ...

In this paper, we propose a new optimization method for yield optimization under simultaneous leakage power and performance limits. The optimization approach ...

Bibliographic details on Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.

Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation · Engineering, Computer Science. ICCAD-2005.

In this paper, we develop an efficient gate-level approach to accurately estimate and optimize the parametric yield, defined by leakage power and delay limits, ...

Robust Circuit Sizing: • Correct for gates and critical paths with large variations. • Apply Pelgrom's Law to reduce delay variations in critical gates.

In this paper, we develop an efficient gate-level approach to accurately estimate and optimize the parametric yield, defined by leakage power and delay limits, ...

The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to ...