The latency of parallel turbo decoder after implementation can be as low as 23.2us at a clock rate of 250 MHz and the throughput can reach up to 6.92Gbps. Index ...
Among all the demands of future TB system, high throughput and low latency are two basic requirements that need to be met. Parallel turbo decoding is a very ...
The latency of parallel turbo decoder after implementation can be as low as 23.2 us at a clock rate of 250 MHz and the throughput can reach up to 6.92 Gbps.
A parallel turbo decoder is designed and implemented in field-programmable gate array (FPGA), a reverse address generator is proposed to reduce the ...
Feb 27, 2021 · Low Latency Parallel Turbo Decoding Implementation for Future Terrestrial Broadcasting Systems. H. Luo, Y. Zhang, W. Li, L. K. Huang, ...
Luo, H. et al. (2018) 'Low Latency Parallel Turbo Decoding Implementation for Future Terrestrial Broadcasting Systems', IEEE Transactions on Broadcasting, 64 (1) ...
Low Latency Parallel Turbo Decoding Implementation for ... - dblp
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Bibliographic details on Low Latency Parallel Turbo Decoding Implementation for Future Terrestrial Broadcasting Systems.
Low Latency Parallel Turbo Decoding Implementation for Future Terrestrial Broadcasting Systems. H. Luo, Y. Zhang, W. Li, L. Huang, J. Cosmas, D. Li, ...
The design resulted in throughput in the range of 80Mbps to 270 Mbps, reducing power consumption to up to 61% as compared to the other state-of-art designs.
In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution ...