Ensuring high test quality while keeping costs low requires increasingly effective memory test solutions. This paper proposes the reuse of self-timing ...

This paper proposes the reuse of self-timing mechanisms that are integrated in many state-of-the-art SRAMs as a programmable DFT solution to improve the defect ...

This paper proposes the reuse of self-timing mechanisms that are integrated in many state-of-the-art SRAMs as a programmable DFT solution to improve the defect ...

Mar 14, 2016 · Ensuring high test quality while keeping costs low requires increasingly effective memory test solutions. This paper proposes the reuse of self- ...

A solution to reduce test escapes is using Designfor-Testability (DFT) circuits and stress tests. Examples of DFT methodologies that can enhance HTD faults' ...

This article presents a detailed analysis of HTD faults in FinFET SRAMs by exploring their sensitization and discussing solutions to improve HTD fault coverage ...

Improving SRAM test quality by leveraging self-timed circuits. Josef Kinseher, Leonardo Bonet Zordan, Ilia Polian, Andreas Leininger.

Josef Kinseher, Leonardo Bonet Zordan, Ilia Polian, Andreas Leininger Improving SRAM test quality by leveraging self-timed circuits. DATE, 2016.

Improving SRAM test quality by leveraging self-timed circuits. Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/date/KinseherZPL16. Home ...

Apr 25, 2024 · Improving SRAM test quality by leveraging self-timed circuits. DATE ... Failure mechanisms and test methods for the SRAM TVC write-assist ...