An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been ...

The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs. Publication: IEICE Transactions on ...

The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs and can be codesigned with the ...

Mar 3, 2009 · SUMMARY. An impedance-isolation technique is proposed for on-chip. ESD protection design for radio-frequency (RF) integrated circuits (ICs),.

Jan 1, 2009 · An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully ...

Dive into the research topics of 'Impedance-isolation technique for ESD protection design in RF integrated circuits'. Together they form a unique fingerprint.

Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits // IEICE Transactions on Electronics. 2009. Vol. E92-C. No. 3. pp. 341-351.

Apr 1, 2020 · This article offers an overview of ESD protection design approaches in an RF environment. Those design approaches cover FET vs BJT-based technologies in both ...

A novel ESD protection design with impedance-isolation technique is proposed and successfully verified in a 0.25-mum CMOS process with top thick metal.

Abstract — A novel ESD protection design with impedance-isolation technique is proposed and successfully verified in a 0.25-µm CMOS process with top thick ...