Yacoub M. El-Ziq, Hamid H. Butt: Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design. ITC 1984: 338-349; 1983.
Designing mixed-mode test pattern generators for minimum-overhead self-testing VLSI circuits ... Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based ...
... Test Methodology for VLSI Data Paths. 327-337 BibTeX · Yacoub M. El-Ziq, Hamid H. Butt: Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design.
This paper presents a comprehensive analysis of the cost effectiveness of using Mixed-Mode Self-Test (MMST) in VLSI based designs.
The justification and impact of using MMST on the products life cycle (semiconductor, factory, & field) at all levels of integration (wafer, PCB, & unit) are ...
H.H. Butt and Y.M. El-Ziq, "Impact of Mixed Mode Generators on. Life Cycle of VLSI Based Designs", Proc. IEEE International. Test Conference, pp. 338-347 ...
There is a slight cost increase due to BIST in design and test development, because of the added time required to design and add pattern generators, response ...
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VLSI Design for Manufacturing: Yield Enhancement. S.W. Director, W. Maly, A.J. Strojwas. ISBN 0-7923-9053-7. Testing and Reliable Design of CMOS Circuits.
Dec 13, 2023 · 84 - Burt, El-ziq - 1984 International Test Conf. - Impact Of Mixed-Mode. Self-Test On Life Cycle Cost Of VLSI Based Designs. -. 277 -. Page 284 ...
This work describes the application of device simulation to opto-electronic and high frequency device design. It begins with a discussion of the tool ...