Mar 28, 2017 · All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. in Proc. Eur. Solid- ...
The GRO is composed of 17 stages of a newly proposed delay cell, which utilizes a gate-switched configuration to solve the charge redistribution problem. The ...
A novel approach called GRO with gate-switch-based delay cell presented in [75] improves the resolution by a factor of 2. Figure 17 shows the structural ...
Computer Science · Digital Converter 100% · Resolution Limit 16% · Ring Oscillator 100% · Sampling Rate 16% · Supply Voltage 16% ...
Feb 5, 2021 · In the simplest TDC architecture, the time resolution is bounded by the CMOS gate delay. Many digital TDCs have been proposed dealing with time ...
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This work presents a comprehensive literature review on different topologies of time‐to‐digital converters (TDCs). A brief history, applications, ...
Jun 15, 2023 · An alternative approach to achieve a sub-gate delay TDC resolution is based on the use of the pulse-shrinking delay line where the TIn in ...
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[PDF] Henzler - 2010 - Time-to-digital converters.pdf - TI E2E
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Thus, the LPI-TDC enables sub gate-delay resolution but can be used as a conventional delay-line TDC without resolution enhancement techniques. Its area can ...
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The converter resolution is required to be around 2ps meanwhile the power consumption should be kept as low as possible.
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Abstract—An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay.
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