Sep 9, 2024 · We propose Chain-of-Descriptions (CoDes), a novel approach to enhance the performance of LLMs for VHDL code generation and summarization tasks.

Sep 9, 2024 · We propose Chain-of-Descriptions (CoDes), a novel approach to enhance the performance of LLMs for VHDL code generation and summarization tasks.

Sep 11, 2024 · This paper discusses how we generate VHDL codes for DSP applications described in dataflow graphs.

This study addresses the problem of how to automatically generate source code that is not only functional, but also well-structured, readable, ...

Jul 20, 2024 · This paper introduces CodeV, a series of open-source instruction-tuned Verilog generation LLMs. Instead of generating descriptions first and then getting the ...

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Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization. P Vijayaraghavan, A Nitsure, C Mackin, L Shi, S Ambrogio, A Haran ...

May 7, 2024 · The Granite series of decoder-only code models for code generative tasks, trained with code written in 116 programming languages are introduced.

Oct 24, 2024 · Two case studies, along with their future outlook, are introduced to highlight the capabilities of LLMs in code repair and testbench generation.

A comprehensive review of LLM researches for code. Works in each category are ordered chronologically.