Abstract: This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL).

Abstract—This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL).

Abstract: This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL).

Nov 9, 2011 · This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop ...

This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL).

A digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL) using a frequency-offset clock.

This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL).

Fingerprint. Dive into the research topics of 'Area efficient phase calibration of a 1.6 GHz multiphase DLL'. Together they form a unique fingerprint.

Area efficient phase calibration of a 1.6 GHz multiphase DLL. Ankur Agrawal; Pavan Kumar Hanumolu; et al. 2011; CICC 2011. Efficient AI System Design with Cross ...

Ankur Agrawal, Kumar Hanumolu, and Gu-Yeon Wei. 9/19/2011. “Area efficient phase calibration of a 1.6 GHz multiphase DLL.” In 2011 IEEE Custom Integrated ...