Then, new circuit design techniques for the CMOS PLA are proposed in the hopes of fulfilling the requirements of high speed and low power at the same time.
Abstract—The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. Operating behaviors of several conventional PLAs are ...
The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. Operating behaviors of several conventional PLAs are analyzed ...
Then, new circuit design techniques for the CMOS PLA are proposed in the hopes of fulfilling the requirements of high speed and low power at the same time.
In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption.
In this tutorial, the author looks at programmable logic array (PLA) fault models and describes various efforts in test generation for conventional PLAs, design ...
In this paper, an ultra high speed dynamic comparator is presented. The PMOS pass transistors are used in the latch and pre-amplifier stage of the comparator.
Missing: PLAs. | Show results with:PLAs.
This paper comparatively reviews sensing circuit designs for the most widely used embedded memory, static random-access memory (SRAM).
Sep 20, 2012 · Low-power High-Speed CMOS I/Os: Design Challenges and Solutions ... O'Mahony, "Modeling and Analysis of High-Speed I/O. Links", IEEE ...
This paper presents an analysis of delay, speed, and comparator considerations, and analytical expressions are derived. Using the equation expressions, we can ...