This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%.

In this paper, a novel low-energy capacitor switching scheme for low power successive approximation register (SAR) analog to digital converter (ADC) is ...

A highly energy-efficiency switching procedure for the capacitor-splitting digital-to-analog converter (DAC) is presented for successive approximation.

This paper presents a low-power 10-bit 130-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 90 nm CMOS process

Jul 1, 2016 · An ultra-low-power high precision switching method for the binary weighted DACs is proposed. ... DAC scheme with high accuracy for SAR ADCs', ...

In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete digital-to-analog converter (DAC)/reference voltage settling. In ...

Feb 14, 2023 · This paper proposed an ultra-low-power successive approximation register analog to digital converter (ADC) for medical implant devices.

Jul 1, 2016 · An ultra-efficient switching method for successive approximation register ADCs is proposed. In this method, the input signals are sampled in ...

Apr 30, 2023 · Abstract—This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital con- verters (ADCs).

The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC.