An architecture of CMOS image sensor tailored to implement a class of robust motion detection algorithms based on recursive operations, allowing sensor's acuity ...

We propose the use of Spiking Neural Networks (SNNs) that are generated from iso-architecture CNNs and trained with quantization-aware gradient descent.

Performance at NT/ST worse than nominal voltage. ♢ can be acceptable in practical situations. ♢ tasks of IoT nodes are often relatively simple.

A new generation of AI accelerator co-designed for compressed neural networks was developed and the manufacturing of ultra-low-power chips will be completed in ...

We propose a hardware–software co-design of the histogram of oriented gradients and the subsequent support vector machine classifier, which can be used to ...

First, we can greatly improve the compute efficiency while simplifying the architecture design by exploiting the synergy between dif- ferent SoC IP blocks.

We propose Impala, an area-efficient, high-throughput, and energy-efficient in-SRAM architecture for automata processing. These three-fold efficiencies are ...

Oct 22, 2024 · This paper presents a low power motion detection algorithm and its system architecture. The proposed architecture uses just one bit data of ...

In this paper, we propose and develop an algorithm-architecture co-designed system, Euphrates, that simultaneously improves the energy-efficiency and ...

Low Power Design is a collection of techniques and methodologies aimed at reducing the overall dynamic and static power consumption of an integrated circuit ...