A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. Abstract: A soft-error-immune, 0.9-ns address ...

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry ; Article #: ; Date of Conference: 02-03 October 1995.

To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, ...

... soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry ... CMOS dynamic RAM with design-for test functions.

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry · Article. November 1996. ·. 86 Reads. ·. 11 Citations.

A soft-error-immune 0.9 ns 1.15 Mb ECL-CMOS SRAM with 30 ps 120k logic gates and on-chip test circuitry. 被引用文献1件. HIGETA K. 収録刊行物. Proc. BCTM.

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry · Engineering, Computer Science. Proceedings of Bipolar/ ...

A Soft Error Immune 0.9 ns 1.15 Mb ECL CMOS SRAM with 30 ps 120k Logic Gates and On Chip Test Circuitry , K. Higeta et al., IEEE 1995 Bipolar Circuits and ...

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM ... A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.

Apr 25, 2024 · A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. IEEE J. Solid State Circuits 31(10) ...