This work explores new hardware architectures for binary and floating-point adders based on numbers' RN-coding.

Jan 9, 2023 · To accomplish this, we have developed a one-bit RN-based adder that allows modular designs, considering an efficient signal propagation to ...

In this work, we propose hardware architectures for binary and floating-point adders, analyzing for the latter its performance in terms of error and resource ...

TL;DR: This work has developed a one-bit RN-based adder that allows modular designs, considering an efficient signal propagation to obtain new architectures ...

A new floating-point adder FPGA-based implementation using RN-coding of numbers · Computers & Electrical Engineering, March 2021 · 10.1016/j.compeleceng.

2021. A new floating-point adder FPGA-based implementation using RN-coding of numbers. T Araujo, MBR Cardoso, EG Nepomuceno, CH Llanos, J Arias-Garcia.

This paper presents the FPGA implementation of a Decimal Floating Point (DFP) adder. The design performs addition on 64-bit operands that use the IEEE 754-2008 ...

In this paper we describe an open source floatingpoint adder and multiplier implemented using a 36-bit custom number format based on radix-16 and optimized ...

Apr 7, 2024 · The issue here is that the output of the division is a float number less than one, and as you know, Verilog does not recognize floating point.

An open source floating-point adder and multiplier implemented using a 36-bit custom number format based on radix-16 and optimized for the 7-series FPGAs from ...