In this paper, we present an Assertion based functional verification methodology for DDR type memory cores. The methodology is based on formulating DDR ...

In this paper, we present an Assertion based functional verification methodology for DDR type memory cores. The methodology is based on formulating DDR ...

The methodology is based on formulating DDR pattern properties extracted from JDEC standard which are then translated to synthesizable DDR Type SVA Protocol ...

Aug 9, 2021 · Bibliographic details on A novel approach for assertion based verification of DDR memory protocols.

Paper: A novel approach for assertion based verification of DDR memory protocols , Author: M Kassem, M Michel, M AbdelSalam, A Salem , Year: 2013 , Benha ...

In this paper, we propose a new method to capture design specifications using a timing diagram tool that documents the captured design specifications in a ...

This paper proposes a new method to capture design specifications using a timing diagram tool that documents the captured design specifications in a Timing ...

The methodology in [26] automatically transforms the timing constraints from the JEDEC standards into system Verilog assertions, which can be used to verify ...

System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on ...

Moustafa Kassem, Marianne Michel, Mohamed Abdelsalam, Ashraf Salem: A novel approach for assertion based verification of DDR memory protocols. FDL 2013: 1-4.