Abstract: We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter ...
We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and ...
Abstract: We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter ...
A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops · T. Konishi, Keisuke Okuno, +2 authors. H.
Kawaguchi,. “A 61-dB SNDR 700 μm2 second-order all-digital TDC with low- jitter frequency shift oscillators and dynamic flipflops,” Symposium on VLSI Circuits, ...
In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and ...
We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and ...
A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops · Computer Science, Engineering. 2012 ...
A 61-dB SNDR 700 µmsecond-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops. T Konishi, K Okuno, S Izumi, M Yoshimoto ...
7. Konishi T., Okumo K., Izumi S., et al: 'A 61 dB SNDR 700 µm second-order all-digital TDC with low-jitter frequency shift oscillator and dynamic flipflops'.
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