The ADC is implemented in 0.18μm 1.8V/3.3V CMOS technology and achieves 72.1dB signal-to-noise ratio (SNR) and 92.6dB spur-free dynamic range (SFDR) with 10.1 ...

Apr 10, 2024 · The ADC is implemented in 0.18μm 1.8V/3.3V CMOS technology and achieves 72.1dB signal-to-noise ratio (SNR) and 92.6dB spur-free dynamic range ( ...

Xiaodan Zhou, Weipeng He, Dongbing Fu, Jianan Wang, Guangbing Chen: A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS ...

The ADC is implemented in 0.18μm 1.8V/3.3V CMOS technology and achieves 72.1dB signal-to-noise ratio (SNR) and 92.6dB spur-free dynamic range (SFDR) with 10.1 ...

Xiaodan Zhou, Weipeng He, Dongbing Fu, Jianan Wang, Guangbing Chen: A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS ...

A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS · Engineering, Physics. IEICE Electronics Express · 2024.

Xiaodan Zhou, Weipeng He, Dongbing Fu, Jianan Wang, Guangbing Chen: A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS ...

... 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR isReferencedBy A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique ...

A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS · Xiaodan Zhou,Weipeng He,Dongbing Fu, Jianan Wang,Guangbing Chen.

A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS. Article de revue Cette œuvre dispose d'un PDF associé dans Matilda.