A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC ; Electronic ISSN: 2376-8606 ; Print ISSN: 0193-6530 ; CD: 0193-6530.
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer ...
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Oct 18, 2010 · Abstract: A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) ...
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented.
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented.
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented.
A 2.1-to-2.8 GHz low-power all-digital PLL with a time-windowed single-shot pulse-controlling 2-step TDC is presented. The test-chip is implemented in 90 nm ...
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo ...
Abstract—A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-dig- ital converter (TDC) is presented.
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC · An All-Digital 12 pJ/Pulse IR-UWB Transmitter Synthesized From a Standard Cell ...
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. Tokairin T., Okada M., Kitsunezuka M., Maeda T., Fukaishi M. Expand. Publication ...