Feb 7, 2006 · This additional dummy capacitor increases the SNR and THD of the ADC by up to 20dB. The proposed ADC is implemented in a 0.13µm 1P 6M CMOS.

Abstract: A 14b multi-bit-per-stage pipelined ADC is implemented in a 0.13μm digital CMOS process. The gain and matching errors of the analog circuitry are ...

At the 14-bit resolution level, a 224-mW pipelined ADC with a 100-MS/s sample rate has been reported in the 0.13-µm CMOS technology [48] , and at 8-bits and 10- ...

A multi-bit 14b pipelined ADC was implemented in a 0.13um digital CMOS Technol- ogy. The gain and matching errors of the analog circuitry are compensated by ...

This paper describes a digitally calibrated pipeline analog-to-digital converter (ADC) implemented in 90 nm CMOS technology with a 1.2 V supply voltage that ...

A 14b pipeline ADC is realized in 90nm CMOS at a 1.2V supply. Enabling techniques are range-scaling in the first pipeline stage with charge-reset and digital ...

A low-power 14-b 100-MS/s analog-to-digital converter (ADC) is described. The prototype ADC achieves low-power consumption and small die area by sharing an ...

Burian, H. Eul “A 14b 100MS/s digitally self calibrated Pipelined ADC in 0.13μm CMOS” ISSCC 2006, Session 12, Feb. 2006. Google Scholar.

This work proposes a 14b 150MS/s CMOS A/D converters (ADC) for software-defined radio systems requiring simul- taneously high-resolution, low-power, ...

A new self-calibration scheme of a high resolution ADC compensating offset and non-linearity errors is presented. The scheme uses redundant bits of a high ...