🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

FPGA based microcomputer sandbox for software and RTL experimentation

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

Custom 64-bit pipelined RISC processor

Implementation of a 2D Convolution Filter using VHDL for FPGAs.

Dual-core 16-bit RISC processor

Music spectrum analyzer implemented on a 7-series FPGA with novel DSP algorithms written in VHDL to accurately bin piano keys to frequency ranges and display in real-time

VHDL : RS232 TX/RX - FPGA ( used for teaching full ppt included )

The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.

Professional VHDL Class Solution - StopWatch

VHDL implemetation of LUX algorithm

play Tetris Video game using PS2-keyboard and VGA monitor and Altera PS2 board

8-bit MISC processor with pipelining

Configurable RISC-V core

My first processor written in HDL language

RTL description of 1D DCT using algebraic integers