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P10 FSI PIB backend on BMC does not access proc > 0 correctly #50

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npiggin opened this issue Dec 22, 2020 · 1 comment
Open

P10 FSI PIB backend on BMC does not access proc > 0 correctly #50

npiggin opened this issue Dec 22, 2020 · 1 comment

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@npiggin
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npiggin commented Dec 22, 2020 •
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This appears like it might be an aspeed fsi scom driver issue because accessing the exact same scom address from the sbefifo backend works correctly. Compare a pdbg threadstatus command on a thread on p3 between sbefifo and default backends:

The successful case (SBE FIFO op PIB driver):
kernel_fsi_probe open(/sys/class/fsi-master/fsi0/slave@00:00/raw)=4 kernel_fsi_probe open(/sys/class/fsi-master/fsi1/slave@03:00/raw)=5 Translating target addr 0xf0040 -> 0x200f0040 on /proc3/pib pib_read[153]: rc = 0, addr = 0x00000000200f0040, data = 0xbc20000000000000, target = /proc3/pib

Failing case (kernel SCOM driver):
kernel_fsi_probe open(/sys/class/fsi-master/fsi0/slave@00:00/raw)=4 PIB open (/dev/scom4) = 5 Translating target addr 0xf0040 -> 0x200f0040 on /proc3/pib kernel_pib_getscom fd=5 kernel_pib_getscom[226]: Failed to read scom addr 0x00000000200f0040 pib_read[153]: rc = 1, addr = 0x00000000200f0040, data = 0x007683e801000000, target = /proc3/pib
@npiggin
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npiggin commented Dec 22, 2020 •
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This problem occurred on a 4s DCM rainier. If you have a core at p3 c2, then the following commands should reproduce:

Using SBE chip ops for xscoms (success case) pdbg -D4 -b sbefifo -p3 -c2 -t0 threadstatus

Using default FSI PIB backend pdbg -D4 -p3 -c2 -t0 threadstatus

(EDIT: With -D4 debugging output)

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