The convex weighted-sum method for multi-objective optimization has the desirable property of not worsening the difficulty of the optimization problem, but can lead to very nonuniform sampling. This paper explains the relationship between the weights ...

As the variations of shrunk processes increasing at rapid rate, the performances of analog/mixed-signal chips remarkably fluctuate. It is necessary to take the yield as a design objective in design optimization. This paper presents a novel method to ...

In traditional yield enhancement approaches, a lot of computation efforts have to be paid first to find the feasible regions and the Pareto fronts, which will become a heavy cost for large analog circuits. In order to reduce the computation efforts, ...

Decoupling capacitor (decap) placement has been widely adopted as an effective way to suppress dynamic power supply noise. Traditional decap budgeting algorithms usually explore the sensitivity-based nonlinear optimizations or conjugate gradient methods,...

Vectorless power grid verification makes it possible to evaluate worst-case voltage drops without enumerating possible current waveforms. Under linear current constraints, the vectorless power grid verification problem can be formulated and solved as a ...

Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates system-level power management. The quantitative understanding of such complex power ...

Conventional CAD methodologies optimize a processor module for correct operation, and prohibit timing violations during nominal operation. In this paper, we propose recovery-driven design, a design approach that optimizes a processor module for a target ...

As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes ...

Transistor sizing is a classic Computer-Aided Design problem that has received much attention in the literature. Due to the increasing importance of process variations in deep sub-micron circuits, nominal circuit tuning is not sufficient, and the sizing ...

This paper proposes comprehensive solutions to the clock tree synthesis problem that provides pre-bond testability for 3D IC designs. In 3D ICs, it is essential to stack only good dies by testing the individual dies before stacking. For the clock ...

Measurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a ...

Modern CMOS technologies employ process-induced stress to improve carrier mobility and increase drive current. This stress has been shown to be strongly layout dependent; however there is a lack of physical models relating potential performance ...

Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. Pin-count reduction and cross-contamination avoidance are key design considerations for practical applications with different droplets being transported and ...

This work proposes a new problem of identifying large and tangled logic structures in a synthesized netlist. Large groups of cells that are highly interconnected to each other can often create potential routing hotspots that require special placement ...

Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard [1]. Several (suboptimal) gate sizing heuristics have been proposed over the ...

Thin-film thermoelectric cooling is a promising technology for mitigating heat dissipation in high performance chips. In this paper, we present an optimization framework for an active cooling system that is comprised of an array of thin-film ...

As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common, to the point of threatening yield rates and product lifetimes. Introspective software mechanisms hold great promise to address these ...

Ultra low power and energy efficiency requirements are common to most IC designs today. Requirements range from extending battery life to operating on harvested energy, with applications ranging from consumer electronics to medical applications. Design ...

Existing approaches to statistical leakage analysis focus only on calculating the mean and variance of the total leakage. In practice, however, what concerns most is the tail behavior of the sum distribution, as it tells that to what extent the design ...

Logic synthesis for soft error mitigation is increasingly important in a wide range of applications of FPGAs. We present R2, an algorithm for rewiring a post-layout LUT-based circuit that reduces the overall criticality of the circuit, where criticality ...