Processing in Memory (PIM) technology is gaining traction with the introduction of several prototype products. However, the interfaces of existing PIM devices hinder CPU performance excessively by delaying normal memory requests for long periods during ...

In this paper, we <italic>first</italic> analyze a real storage system consisting of 72 SSDs utilizing either <italic>Hardware RAID</italic> (HW-RAID) or <italic>Software RAID</italic> (SW-RAID), and show that SW-RAID is up to 7&#x00D7; faster. We then ...

Modern computer designs support composite prefetching, where multiple prefetcher components are used to target different memory access patterns. However, multiple prefetchers competing for resources can sometimes hurt performance, especially in many-core ...

Due to emerging workloads that require high memory bandwidth, Processing-in-Memory (PIM) has gained significant attention and led several industrial PIM products to be introduced which are integrated with conventional computing systems. This letter ...

DRAM memory reliability is increasingly a concern as recent studies found. In this letter, we propose RAIMD (Redundant Array of Independent Memory Devices), an energy-efficient memory organization with RAID-like error protection. In this organization, ...

Row Hammer (RH) is a circuit-level phenomenon where repetitive activation of a DRAM row causes bit-flips in adjacent rows. Prior studies that rely on extra refreshes to mitigate RH vulnerability demonstrate that bit-flips can be prevented effectively. ...

As non-volatile memory (NVM) technologies advance, commercial NVDIMM devices have been made readily available for various computing systems. To efficiently utilize the high-density and high-capacity of NVM, the latest Xeon CPUs support a special <italic>...

Recent DNA <italic>pre-alignment</italic> filter designs employ DRAM for storing the reference genome and its associated meta-data. However, DRAM incurs increasingly high energy consumption of background and refresh energy as devices scale. To overcome ...

Emerging Non-Volatile Memories (NVMs) are entering the mainstream market. With attractive performance, high density, and near-zero idle power, emerging NVMs are promising contenders to build future memory systems. On the other hand, their limited write ...

To mitigate the impact of non-deterministic media access latencies in new memory technology devices, a recently proposed Non-Volatile Dual In-line Memory Module (NVDIMM) standard, NVDIMM-P uses novel out-of-order transaction commands. The previous DRAM ...

Data copy is a widely-used memory operation in many programs and operating system services. In conventional computers, data copy is often carried out by two separate read and write transactions that pass data back and forth between the DRAM chip and the ...

Instruction cache misses are the critical performance bottleneck in the execution of recent workloads such as Web applications written in JavaScript and server applications. Although various instruction prefetchers have been proposed to reduce the misses, ...

Memristors are emerging Non-Volatile Memories (NVMs) that are promising for building future memory systems. Unlike DRAM, memristors are non-volatile, i.e., they can retain data after power loss. In contrast to DRAM where each cell is associated with a ...

Power and energy consumed by main memory systems in data-center servers have increased as the DRAM capacity and bandwidth increase. Particularly, <monospace>background power</monospace> accounts for a considerable fraction of the total DRAM power ...

Die-stacked memories that integrate multiple DRAM dies into the processor package have reduced the interface bottleneck and improved efficiency, but demands for memory capacity and bandwidth remain unfulfilled. Additionally, the introduction of memory ...

Instruction cache misses are a significant source of performance degradation in server workloads because of their large instruction footprints and complex control flow. Due to the importance of reducing the number of instruction cache misses, there has ...

The modern system-on-chip (SoC) of the current exascale computing era is complex. These SoCs not only consist of several general-purpose processing cores but also integrate many specialized hardware accelerators. Three common coherency interfaces are used ...

Computer systems using DRAM are exposed to row-hammering attacks, which can flip data in a DRAM row without directly accessing a row but by frequently activating its adjacent ones. There have been a number of proposals to prevent row-hammering, but they ...

Memory-intensive workloads operate on massive amounts of data that cannot be captured by last-level caches (LLCs) of modern processors. Consequently, processors encounter frequent off-chip misses, and hence, lose significant performance potential. One ...

Scaling down DRAM technology degrades cell reliability due to increased coupling between adjacent DRAM cells, commonly referred to as crosstalk. Moreover, high access frequency of certain cells (hot cells) may cause data loss in neighboring cells in ...