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- ArticleOctober 2006
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesisPages 259–264https://doi.org/10.1145/1176254.1176316This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both ...
- ArticleOctober 2006
SHAPES:: a tiled scalable software hardware architecture platform for embedded systems
CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesisPages 167–172https://doi.org/10.1145/1176254.1176297Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires". A ...
- ArticleOctober 2006
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesisPages 142–147https://doi.org/10.1145/1176254.1176289In this paper, we present a methodology to specialize the routing algorithm in routing table based NoC routers. It tries to maximize the communication performance while ensuring deadlock free routing for an application. We demonstrate through analysis ...