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- ArticleApril 1982
Resource allocation in rectangular SW banyans
This paper presents an algorithm for the formation of configurations connecting processors to memory and I/O devices on rectangular SW banyan networks with equivalent processor resources as the base nodes and equivalent memory and I/O resources as the ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
Finding an extremum in a network
We propose a method for implementing “the election process” - finding an extrema of values computed in a multiprocessor network. It operates in an average time less than Log2(N), for a network of size N. It requires a single register, memory cell, or ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
Probabilistic analysis of a crossbar switch
This paper presents a probabilistic analysis of a crossbar switch interconnection network. A crossbar switch can be used to interconnect various combinations of computer subsystems. In the analysis below it is assumed, without loss of generality, that ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
Effects of cache coherency in multiprocessors
In many commercial multiprocessor systems, each processor accesses the memory through a private cache. One problem that could limit the extensibility of the system and its performance is the enforcement of cache coherence. A mechanism must exist which ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
Duplication of packets and their detection in X.25 communication protocols
In the context of X.25 communication protocols, this paper is concerned with the process of duplication of packets at the frame level, and with their detection at the packet level. With suitable constraints involving
(i) the window sizes used at both ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
A shared resource algorithm for distributed simulation
We propose a distributed simulation method which is particularly well suited for the simulation of large synchronous networks. In general, distributed simulation has significant potential for alleviating the time and memory constraints often encountered ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
A recursive computer architecture for VLSI
We present a general-purpose computer architecture based on the concept of recursion, suitable for VLSI computer systems built from replicated (LEGO-like) computing elements. The recursive computer architecture is defined by presenting a program ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
On the semantic structure of information - A proposal of the abstract storage architecture
An important strategy to enhance both the reliability and performance of high-level program execution is to have computer architecture provided with the mechanisms, such as i) to address information in a unified manner regardless of the structure and/or ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
Fault-tolerant wafer-scale architectures for VLSI
The basic problem which limits both yields and chip sizes is the fact that circuits created using current design techniques will not function correctly in the presence of even a single flaw of sufficient size anywhere on the chip. In this work we ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
Design of a 2 × 2 fault-tolerant switching element
This paper describes the architecture of a 2 × 2 fault-tolerant switching element which can be used to modularly construct interconnection networks for multi-processing and local computer networking. The switching element uses distributed control and ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
Towards a family of languages for the design and implementation of machine architectures
In recent years, increases in complexity of hardware/firmware systems, and the concern for systems reliability have resulted in growing interest in methodologies and tools for the design, description and verification of computer systems. A vital ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
A logic simulation machine
Special-purpose CAD hardware is increasingly being considered as a means to meet the challenge posed to conventional (software-based) CAD tools by the growing complexity of VLSI circuits. In this paper we describe the architecture of a logic simulation ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
A control processor for a reconfigurable array computer
The problems of resource allocation, configuration and reconfiguration and network control must be solved before reconfigurable array computers can be effectively utilized. The interconnection networks proposed for these systems vary so that there has ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
The Gamma network: A multiprocessor interconnection network with redundant paths
The Gamma network is an interconnection network connecting N=2' inputs to N outputs. It consists of log2N stages with N switches per stage, each of which is a 3 input, 3 output crossbar. The stages are linked via “power of two” and identity connections ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
Asynchronous and clocked control structures for VLSI based interconnection networks
A central issue in the design of multiprocessor systems is the interconnection network which provides communications paths between the processors. For large systems, high bandwidth interconnection networks will require numerous 'network chips' with each ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
VLSI architectures for high speed recognition of context-free languages and finite-state languages
This paper presents two VLSI architectures for the recognition of context-free languages and finite-state languages. The architecture for context-free languages consists of n(n+1)/2 identical cells and it is capable of recognizing an input string of ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
The NYU Ultracomputer—designing a MIMD, shared-memory parallel machine (Extended Abstract)
We present the design for the NYU Ultracomputer, a shared-memory MIMD parallel machine composed of thousands of autonomous processing elements. This machine uses an enhanced message switching network with the geometry of an Omega-network to approximate ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
Measurement and analysis of instruction use in the VAX-11/780
This paper reports measurements of instruction set use on the VAX-11/780 computer. A hardware monitor was used to measure the frequency and time taken by each VAX instruction. Data from benchmark programs, a compiler, a linker, and a synthetic ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3 - ArticleApril 1982
RISC assessment: A high-level language experiment
We present the result of an informal experiment comparing the performance of one Reduced Instruction Set Computer, RISC I, to five traditional computers, VAX-11/780, PDP-11/70, BBN C/70, MC68000, and Z8000, in a high-level language environment. ...
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ACM SIGARCH Computer Architecture News: Volume 10 Issue 3