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- research-articleJanuary 2020
Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools
ASPDAC '20: Proceedings of the 25th Asia and South Pacific Design Automation ConferencePages 351–356https://doi.org/10.1109/ASP-DAC47756.2020.9045734Chiplet integration using 2.5D packaging is gaining popularity nowadays which enables several interesting features like heterogeneous integration and drop-in design method. In the traditional die-by-die approach of designing a 2.5D system, each chiplet ...
- research-articleMay 2019
RDTA: An Efficient Routability-Driven Track Assignment Algorithm
GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSIPages 315–318https://doi.org/10.1145/3299874.3318026This paper presents a routability-driven track assignment algorithm (RDTA) to efficiently estimate routability. Routability has become a very challenging issue in modern IC design and it can be effectively estimated by routing congestion. Track ...
- research-articleJune 2010
Global routing and track assignment for flip-chip designs
DAC '10: Proceedings of the 47th Design Automation ConferencePages 90–93https://doi.org/10.1145/1837274.1837298This paper describes a solution for global routing and track assignment of flip-chip I/O nets. Voronoi Diagram (VD) is used to partition the open routing space and the geometrical properties of VD graph are exploited to create global routing channels ...
- ArticleJanuary 1995
A general graph theoretic framework for multi-layer channel routing
In this paper we propose a general framework for viewing a class of heuristics for track assignment in channel routing from a purely graph theoretic angle. Within this framework we propose algorithms for computing routing solutions using optimal or near ...