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- ArticleSeptember 2004
Non-Manhattan maze routing
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system designPages 260–265https://doi.org/10.1145/1016568.1016637The availability of multiple metal layers in modern IC processes raises the possibility of using non-Manhattan routing on some of the layers in order to reduce the average interconnect length, and thus improve performance and routability. In this paper, ...
- ArticleJune 2004
Fast and flexible buffer trees that navigate the physical layout environment
DAC '04: Proceedings of the 41st annual Design Automation ConferencePages 24–29https://doi.org/10.1145/996566.996575Buffer insertion is an increasingly critical optimization for achieving timing closure, and the number of buffers required increases significantly with technology migration. It is imperative for an automated buffer insertion algorithm to be able to ...
- ArticleApril 2004
A fast algorithm for identifying good buffer insertion candidate locations
ISPD '04: Proceedings of the 2004 international symposium on Physical designPages 47–52https://doi.org/10.1145/981066.981076Van Ginneken's algorithm [18] for performing buffer insertion is a classic in the field, since it optimally solves the problem subject to a set of fixed buffer insertion candidate locations for a given Steiner topology. The generation of these candidate ...
- articleNovember 2003
CNB: a critical-network-based timing optimization method for standard cell global routing
Journal of Computer Science and Technology (JCST), Volume 18, Issue 6Pages 732–738https://doi.org/10.1007/BF02945461A novel method, named critical-network-based (CNB), for timing optimization in global routing is presented in this paper. The essence of this method is different from that of the typical existing ones, named nets-based (NB) and critical-path-based (CPB)...
- articleSeptember 2003
SSTT: efficient local search for GSI global routing
Journal of Computer Science and Technology (JCST), Volume 18, Issue 5Pages 632–639https://doi.org/10.1007/BF02947123In this paper, a novel global routing algorithm is presented for congestion optimization based on efficient local search, named SSTT (search space traversing technology). This method manages to traverse the whole search space. A hybrid optimization ...
- articleAugust 2003
An efficient hierarchical timing-driven Steiner tree algorithm for global routing
Integration, the VLSI Journal (INTG), Volume 35, Issue 2Pages 69–84https://doi.org/10.1016/S0167-9260(03)00029-4In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as the goal. The algorithm uses heuristic approach to decompose the problem of ...
- ArticleJune 2003
Improved global routing through congestion estimation
DAC '03: Proceedings of the 40th annual Design Automation ConferencePages 28–31https://doi.org/10.1145/775832.775842In this paper, we present a new method to improve global routing results. By using an amplified congestion estimate to influence a rip-up and reroute approach, we obtain substantial reductions in total congestion. In comparisons with a recently ...
- ArticleApril 2003
Congestion reduction in traditional and new routing architectures
GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSIPages 211–214https://doi.org/10.1145/764808.764862In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, routing, and routing architecture all contribute. Previous work has shown that ...
- research-articleJanuary 2003
General Models and a Reduction Design Technique for FPGA Switch Box Designs
IEEE Transactions on Computers (ITCO), Volume 52, Issue 1Pages 21–30https://doi.org/10.1109/TC.2003.1159751An FPGA switch box is said to be hyper-universal if it is detailed-routable for any set of multipin nets specifying a routing requirement over the switch box. Comparing with the known universal switch modules, where only 2-pin nets are considered, the ...
- articleOctober 2002
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 7, Issue 4Pages 664–693https://doi.org/10.1145/605440.605449Incremental physical CAD is encountered frequently in the so-called engineering change order (ECO) process in which design changes are made typically late in the design process in order to correct logical and/or technological problems in the circuit. ...
- ArticleApril 2002
Early probabilistic noise estimation for capacitively coupled interconnects
SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect predictionPages 77–83https://doi.org/10.1145/505348.505365One of the critical challenges in today's high performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools [1, 7} are effective at analyzing and identifying noise in the post-route design ...
- articleAugust 1998
Layout Driven Selection and Chaining of Partial Scan Flip-Flops
Journal of Electronic Testing: Theory and Applications (JELT), Volume 13, Issue 1Pages 19–27https://doi.org/10.1023/A:1008381015527In an era of sub-micron technology, routing is becoming a dominant factor in area, timing, and power consumption. In this paper, we study the problem of selection and chaining of scan flip-flops with the objective of achieving minimum routing area ...
- ArticleMay 1998
Delay-optimal technology mapping by DAG covering
DAC '98: Proceedings of the 35th annual Design Automation ConferencePages 348–351https://doi.org/10.1145/277044.277142We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that ...
- ArticleMay 1998
Efficient Boolean division and substitution
DAC '98: Proceedings of the 35th annual Design Automation ConferencePages 342–347https://doi.org/10.1145/277044.277141Bo ole andivision, and henc eBo ole ansubstitution, produc es better result than algebraic division and substitution. However, due to the lack of an efficient Bo ole andivision algorithm, Bo ole ansubstitution has rarely b een used. We present an ...
- ArticleMay 1998
M32: a constructive multilevel logic synthesis system
DAC '98: Proceedings of the 35th annual Design Automation ConferencePages 336–341https://doi.org/10.1145/277044.277140We describe a new constructive multilevel logic synthesis system that integrates the traditionally separate technology-independent and technology-dependent stages of modern synthesis tools. Dubbed M32, this system is capable of generating circuits ...
- ArticleMay 1998
Optimal FPGA mapping and retiming with efficient initial state computation
DAC '98: Proceedings of the 35th annual Design Automation ConferencePages 330–335https://doi.org/10.1145/277044.277139For sequential circuits with given initial states, new equivalent initial states must be computed for retiming, which unfortunately is NP-hard. In this paper we propose a novel polynomial time algorithm for optimal FPGA mapping with forward retiming to ...
- ArticleMay 1998
Media architecture: general purpose vs. multiple application-specific programmable processor
DAC '98: Proceedings of the 35th annual Design Automation ConferencePages 321–326https://doi.org/10.1145/277044.277136In this paper we report a framework that makes it possible for a designer to rapidly explore the application-specific programmable processor design space under area constraints. The framework uses a production-quality compiler and simulation tools to ...
- ArticleMay 1998
A programming environment for the design of complex high speed ASICs
DAC '98: Proceedings of the 35th annual Design Automation ConferencePages 315–320https://doi.org/10.1145/277044.277135A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiv er is used as a driv er example. Compact descriptions, combined with efficient sim ulationand syn thesis strategies are ...
- ArticleMay 1998
A methodology for guided behavioral-level optimization
DAC '98: Proceedings of the 35th annual Design Automation ConferencePages 309–314https://doi.org/10.1145/277044.277134Optimization at the early stages of design are crucial. However, due to an overwhelming number of design and optimization options, design exploration is often conducted in a qualitative, ad-hoc manner. This paper presents a methodology and interactive ...
- ArticleMay 1998
Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis
DAC '98: Proceedings of the 35th annual Design Automation ConferencePages 303–308https://doi.org/10.1145/277044.277133It is well understood that frequency independent lumped-element circuits can be used to accurately model proximity and skin effects in transmission lines [7]. Furthermore, it is also understood that these circuits can be synthesized knowing only the ...