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- short-paperJune 2024
A P&R Co- Optimization Engine for Reducing Congestion
GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024Pages 525–528https://doi.org/10.1145/3649476.3658796Placement and routing (P&R) are two crucial stages in the physical design process to optimize different objectives. For instance, placement often focuses on optimizing the half-perimeter wirelength (HPWL) and estimated congestion while routing attempts ...
- research-articleMarch 2024
GPU/ML-Enhanced Large Scale Global Routing Contest
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPages 269–274https://doi.org/10.1145/3626184.3639693Modern VLSI design flows demand scalable global routing techniques applicable across diverse design stages. In response, the ISPD 2024 contest pioneers the first GPU/ML-enhanced global routing competition, selecting advancements in GPU-accelerated ...
- research-articleApril 2024
V-GR: 3D Global Routing with via Minimization and Multi-Strategy Rip-Up and Rerouting
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferencePages 963–968https://doi.org/10.1109/ASP-DAC58780.2024.10473939In VLSI, a large number of vias may reduce manufacturability, degrade circuit performance, and increase layout area required for interconnection. In this paper, we propose a 3D global router V-GR, which considers minimizing the number of vias. V-GR uses ...
- research-articleSeptember 2023
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 28, Issue 5Article No.: 73, Pages 1–25https://doi.org/10.1145/3590768Routing congestion is one of the many factors that need to be minimized during the physical design phase of large integrated circuits. In this article, we propose a novel congestion estimation method, called MEDUSA, that consists of three parts: (1) a ...
- research-articleSeptember 2023
Global Interconnect Optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 28, Issue 5Article No.: 72, Pages 1–24https://doi.org/10.1145/3587044We propose a new comprehensive solution to global interconnect optimization. Traditional buffering algorithms mostly insert repeaters on a net-by-net basis based on slacks and possibly guided by global wires.
We show how to integrate routing congestion, ...
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- short-paperJune 2023
RL-Ripper:: A Framework for Global Routing Using Reinforcement Learning and Smart Net Ripping Techniques
GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023Pages 197–201https://doi.org/10.1145/3583781.3590312Physical designers have been using heuristics to solve challenging problems in routing. However, these heuristic solutions are not adaptable to the ever-changing fabrication demands and their effectiveness is limited by the experience and creativity of ...
- research-articleMay 2023
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 28, Issue 4Article No.: 51, Pages 1–19https://doi.org/10.1145/3564930A multiterminal obstacle-avoiding pathfinding approach is proposed. The approach is inspired by deep image learning. The key idea is based on training a conditional generative adversarial network (cGAN) to interpret a pathfinding task as a graphical ...
- short-paperJune 2022
An Efficient Maze Routing Algorithm for Fast Global Routing
GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI 2022Pages 169–172https://doi.org/10.1145/3526241.3530360Maze routing remains the most time-consuming step for modern global routers. Previous works accelerate the maze routing by routing multiple regions or nets simultaneously. This paper presents a novel parallel maze router with bidirectional path search ...
- research-articleMay 2022
CR&P: an efficient co-operation between routing and placement
- Erfan Aghaeekiasaraee,
- Aysa Fakheri Tabrizi,
- Tiago Augusto Fontana,
- Renan Netto,
- Sheiny Fabre Almeida,
- Upma Gandhi,
- José Luís Güntzel,
- David Westwick,
- Laleh Behjat
DATE '22: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in EuropePages 772–777Placement and Routing (P&R) are two main steps of the physical design flow implementation. Traditionally, because of their complexity, these two steps are performed separately. But the implementation of the physical design in advanced technology nodes ...
- research-articleJanuary 2022
SPRoute 2.0: A Detailed-Routability-Driven Deterministic Parallel Global Router with Soft Capacity
ASPDAC '22: Proceedings of the 27th Asia and South Pacific Design Automation ConferencePages 586–591https://doi.org/10.1109/ASP-DAC52403.2022.9712557Global routing has become more challenging due to advancements in the technology node and the ever-increasing size of chips. Global routing needs to generate routing guides such that (1) routability of detailed routing is considered and (2) the routing ...
- research-articleNovember 2020
A neural network that routes ICs: late breaking results
DAC '20: Proceedings of the 57th ACM/EDAC/IEEE Design Automation ConferenceArticle No.: 253, Pages 1–2A global router is proposed that learns from routed circuits and autonomously routes unseen layouts. The uniqueness of this approach is in redefining the global routing as a classical image-to-image processing problem. The imaging problem is efficiently ...
- research-articleMay 2020
A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects
ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 16, Issue 3Article No.: 31, Pages 1–28https://doi.org/10.1145/3384214With extreme miniaturization of traditional CMOS devices in deep sub-micron design levels, the delay of a circuit, as well as power dissipation and area are dominated by interconnections between logic blocks. Interconnect today is causing major problems ...
- research-articleMarch 2020Honorable Mention
Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network
ISPD '20: Proceedings of the 2020 International Symposium on Physical DesignPages 57–64https://doi.org/10.1145/3372780.3375557In this paper, we have proposed a machine-learning framework to predict the DRC-violation map of a given design resulting from its detailed routing based on the congestion report resulting from its global routing. The proposed framework utilizes ...
- research-articleJune 2020
Explainable DRC hotspot prediction with random forest and SHAP tree explainer
DATE '20: Proceedings of the 23rd Conference on Design, Automation and Test in EuropePages 1151–1156With advanced technology nodes, resolving design rule check (DRC) violations has become a cumbersome task, which makes it desirable to make predictions at earlier stages of the design flow. In this paper, we show that the Random Forest (RF) model is ...
- research-articleApril 2019
ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules
ISPD '19: Proceedings of the 2019 International Symposium on Physical DesignPages 147–151https://doi.org/10.1145/3299902.3311067Detailed routing becomes the most complicated and runtime consuming stage in the physical design flow as technology nodes advance. Due to the inaccessibility of advanced routing rules and industrial designs, it is hard to conduct detailed routing ...
- research-articleMay 2018
A Comparative Study of Local Net Modeling Using Machine Learning
GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSIPages 273–278https://doi.org/10.1145/3194554.3194579Local nets are by default ignored during global routing but can contribute to a high percentage (up to 30%) of total number of nets in the design. Prior work proposed simple models for how local nets are routed and showed benefits such as better ...
- research-articleMay 2018
Electromigration Design Rule aware Global and Detailed Routing Algorithm
GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSIPages 267–272https://doi.org/10.1145/3194554.3194567Electromigration (EM) in interconnects is becoming a major concern as the scaling of technology nodes. Electromigration affects chip performance and signal integrity seriously by generating shorts or opens, and then shortens the life-time of integrated ...
- short-paperMay 2016
Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees
GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSIPages 263–268https://doi.org/10.1145/2902961.2903036With extreme miniaturization of traditional CMOS devices in deep sub-micron design levels, the delay of a circuit, as well as power dissipation and area are dominated by interconnections between logic blocks. In an attempt to search for alternative ...
- research-articleDecember 2015
FuzzRoute: A Thermally Efficient Congestion-Free Global Routing Method for Three-Dimensional Integrated Circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 1Article No.: 1, Pages 1–38https://doi.org/10.1145/2767127The high density of interconnects, closer proximity of modules, and routing phase are pivotal during the layout of a performance-centric three-dimensional integrated circuit (3D IC). Heuristic-based approaches are typically used to handle such NP-...
- tutorialNovember 2015
Global Routing with Inherent Static Timing Constraints
ICCAD '15: Proceedings of the IEEE/ACM International Conference on Computer-Aided DesignPages 102–109We show how to incorporate global static timing constraints into global routing. Our approach is based on the min-max resource sharing model that proved successful for global routing in theory and practice. Static timing constraints are modeled by a ...