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- ArticleOctober 1997
Functional Fault Simulation of VHDL Gate Level Models
A method of fault injection and fault simulation is proposed. A gate level circuit is modified to include logic gates where faults are to be injected. Values assigned to the inputs of the new additions of the circuit have the effect of injecting stuck-...
- ArticleMarch 1996
VHDL description of self-checking logic circuits
The mainstream of current digital circuit design strategy is top-down, where the design process is divided into many phases. A designer starts with a high level description of a circuit, e.g. VHDL, and goes through the design phases to reach mask layout ...