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- research-articleJuly 2024
SecurityCloak: Protection against cache timing and speculative memory access attacks
Journal of Systems Architecture: the EUROMICRO Journal (JOSA), Volume 150, Issue Chttps://doi.org/10.1016/j.sysarc.2024.103107AbstractMicroarchitectural innovations such as deep cache hierarchies, out-of-order execution, branch prediction and speculative execution in modern processors have made possible to meet ever-increasing demands for performance. However, these innovations ...
- research-articleDecember 2023
Phantom: Exploiting Decoder-detectable Mispredictions
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on MicroarchitecturePages 49–61https://doi.org/10.1145/3613424.3614275Violating the Von Neumann sequential processing principle at the microarchitectural level is commonplace to reach high performing CPU hardware — violations are safe as long as software executes correctly at the architectural interface. Speculative ...
- research-articleFebruary 2023
SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V
ACM Transactions on Architecture and Code Optimization (TACO), Volume 20, Issue 1Article No.: 15, Pages 1–26https://doi.org/10.1145/3566053In modern processors, speculative execution has significantly improved the performance of processors, but it has also introduced speculative execution vulnerabilities. Recent defenses are based on the delayed execution to block various speculative side ...
- research-articleJanuary 2023
Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers
ASPLOS 2023: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2Pages 354–369https://doi.org/10.1145/3575693.3575700Side-channel attacks pose serious threats to many security models, especially sandbox-based browsers. While transient-execution side channels in out-of-order processors have previously been blamed for vulnerabilities such as Spectre and Meltdown, we ...
- research-articleJanuary 2023
A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment
Computers and Electrical Engineering (CENG), Volume 105, Issue Chttps://doi.org/10.1016/j.compeleceng.2022.108546AbstractThe trust execution environment (TEE) provides a safe region, also known as a secret enclave, for executing private programs that need protection. This work proposed a cross-process exploitation scheme for conducting the cache side-channel attack,...
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Highlights- Replicate cache side-channel attack variants on an FPGA with the RISC-V processor’s configuration.
- Implement a cross-process side-channel attack via cache scenario for the first time on the RISC-V platform.
- Experiment with cache ...
- research-articleJanuary 2022
A Review on Vulnerabilities to Modern Processors and its Mitigation for Various Variants
Procedia Computer Science (PROCS), Volume 215, Issue CPages 91–97https://doi.org/10.1016/j.procs.2022.12.010AbstractRecently, security researchers have found two hardware security vulnerabilities namely Spectre and Meltdown, related to computer memory. They are not singular, many variants of these two vulnerabilities are being a head ache for secure hardware ...
- ArticleNovember 2021
Verifying Secure Speculation in Isabelle/HOL
AbstractSecure speculation is an information flow security hyperproperty that prevents transient execution attacks such as Spectre, Meltdown and Foreshadow. Generic compiler mitigations for secure speculation are known to be insufficient for eliminating ...
- research-articleNovember 2021
Variability Analysis of SBOX With CMOS 45 nm Technology
Wireless Personal Communications: An International Journal (WPCO), Volume 124, Issue 1Pages 671–682https://doi.org/10.1007/s11277-021-09377-0AbstractThe consistent scaling of metal-oxide-semiconductor field-effect transistor devices lead to parameter variations which become a significant design challenge for the researchers and designers. This variation deviates the design parameter from ...
- research-articleNovember 2021
Exorcising Spectres with Secure Compilers
CCS '21: Proceedings of the 2021 ACM SIGSAC Conference on Computer and Communications SecurityPages 445–461https://doi.org/10.1145/3460120.3484534ttackers can access sensitive information of programs by exploiting the side-effects of speculatively-executed instructions using Spectre attacks. To mitigate these attacks, popular compilers deployed a wide range of countermeasures whose security, ...
- research-articleOctober 2021
GhostMinion: A Strictness-Ordered Cache System for Spectre Mitigation
MICRO '21: MICRO-54: 54th Annual IEEE/ACM International Symposium on MicroarchitecturePages 592–606https://doi.org/10.1145/3466752.3480074Out-of-order speculation, a technique ubiquitous since the early 1990s, remains a fundamental security flaw. Via attacks such as Spectre and Meltdown, an attacker can trick a victim, in an otherwise entirely correct program, into leaking its secrets ...
- research-articleOctober 2021
BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster
RAID '21: Proceedings of the 24th International Symposium on Research in Attacks, Intrusions and DefensesPages 103–118https://doi.org/10.1145/3471621.3471857Recent research has revealed an ever-growing class of microarchitectural attacks that exploit speculative execution, a standard feature in modern processors. Proposed and deployed countermeasures involve a variety of compiler updates, firmware updates, ...
- research-articleApril 2021
Reproducing Spectre Attack with gem5: How To Do It Right?
EuroSec '21: Proceedings of the 14th European Workshop on Systems SecurityPages 15–20https://doi.org/10.1145/3447852.3458715As processors become more and more complex due to performance optimizations and energy savings, new attack surfaces raise. We know that the micro-architecture of a processor leaks some information into the architectural domain. Moreover, some mechanisms ...
- research-articleJanuary 2021
Automatically eliminating speculative leaks from cryptographic code with blade
- Marco Vassena,
- Craig Disselkoen,
- Klaus von Gleissenthall,
- Sunjay Cauligi,
- Rami Gökhan Kıcı,
- Ranjit Jhala,
- Dean Tullsen,
- Deian Stefan
Proceedings of the ACM on Programming Languages (PACMPL), Volume 5, Issue POPLArticle No.: 49, Pages 1–30https://doi.org/10.1145/3434330We introduce Blade, a new approach to automatically and efficiently eliminate speculative leaks from cryptographic code. Blade is built on the insight that to stop leaks via speculative execution, it suffices to cut the dataflow from expressions that ...
- research-articleJune 2019
SpectreGuard: An Efficient Data-centric Defense Mechanism against Spectre Attacks
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019Article No.: 61, Pages 1–6https://doi.org/10.1145/3316781.3317914Speculative execution is an essential performance enhancing technique in modern processors, but it has been shown to be insecure. In this paper, we propose SpectreGuard, a novel defense mechanism against Spectre attacks. In our approach, sensitive ...
- ArticleApril 2019
Model Checking Speculation-Dependent Security Properties: Abstracting and Reducing Processor Models for Sound and Complete Verification
AbstractThough modern microprocessors embed several hardware security mechanisms, aimed at guaranteeing confidentiality and integrity of sensible data, recently disclosed attacks such as Spectre and Meltdown witness weaknesses with potentially great ...
- research-articleApril 2010
Compact models for memristors based on charge-flux constitutive relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 29, Issue 4Pages 590–598https://doi.org/10.1109/TCAD.2010.2042891This paper introduces compact models for memristors. The models are developed based on the fundamental constitutive relationships between charge and flux of memristors. The modeling process, with a few simple steps, is introduced. For memristors with ...
- articleAugust 2006
A designer's approach to device mismatch: Theory, modeling, simulation techniques, scripting, applications and examples
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 48, Issue 2Pages 95–106https://doi.org/10.1007/s10470-006-5367-2This paper presents the author's integrated approach to custom device mismatch simulations, and is intended for both the design and the modeling communities. It provides the means for the generation of Monte Carlo mismatch models, when foundry libraries ...