High-level synthesis (HLS) aims at democratizing custom hardware acceleration with highly abstracted software-like descriptions. However, efficient accelerators still require substantial low-level hardware optimizations, defeating the HLS intent. In the ...

FPGAs, characterized by their low power consumption and swift response, are ideally suited for parallel computations associated with object detection tasks, making them a popular choice for target detection and neural network acceleration. ...

• Parallel computation boosts speed and efficiency in convolutional layers.
• Integrated parallel processing enhances convolution activation pooling.
• Efficient memory management reduces read/write time for feature layers.
• ...

The convolution layer in a convolutional neural network (CNN) is highly computationally intensive. It is crucial to design reusable low-cost hardware IP for convolutional layer for enabling hardware-based feature extraction. However, the ...

The increasing usage of image processing applications in modern technological environments is driven by their ability to enhance visual quality in diverse applications, from social media to medical imaging. The design of these cores as dedicated ...

Rapid growth in data size poses significant computational and memory challenges to data processing. FPGA accelerators and near-storage processing have emerged as compelling solutions for tackling the growing computational and memory requirements. Many ...

In recent years, domain-specific accelerators (DSAs) have gained popularity for applications such as deep learning and autonomous driving. To facilitate DSA designs, programmers use high-level synthesis (HLS) to compile a high-level description written ...

Most FPGA boards in the HPC domain are well-suited for parallel scaling because of the direct integration of versatile and high-throughput network ports. However, the utilization of their network capabilities is often challenging and error-prone ...

A Bayesian network is a powerful tool for representing uncertainty in data, offering transparent and interpretable inference, unlike neural networks’ black-box mechanisms. To fully harness the potential of Bayesian networks, it is essential to learn the ...

Rising global fire incidents necessitate effective solutions, with forest surveillance emerging as a crucial strategy. This paper proposes a complete solution using technology that integrates visible and infrared spectrum images through Unmanned ...

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• Real-time detection using UAVs for people and cars in forests based on deep learning.
• 4-channel object detection model with RGB and IR, for low-visibility environments.
• A new annotated and aligned image dataset with four channels (...

The Media-over-QUIC Transport (MOQT) is an emerging application-layer protocol designed for low-latency media ingestion and distribution. It is applicable in both browser scenarios (i.e., HTTP/3 Web-Transport) and non-browser settings (i.e., raw QUIC) ...

The Sparse Matrix Vector (SpMV) multiplication kernel is a key component of many high-performance computing applications, but at the same time one of the most challenging to optimize, primarily due to its low flop-per-byte ratio and irregular ...

This paper presents a novel dual defense security methodology for fault detectable reusable hardware intellectual property (IP) core against reverse engineering and piracy using multi-cut based architectural obfuscation and handprint biometric ...

• A novel dual defense security methodology for fault detectable reusable hardware IP core.
• Multi-cut based architectural obfuscation and handprint biometric signature-based approach.
• Ensures protection of fault secured IPs against ...

DASH-IF Content Steering [4] (to be soon published as ETSI TS 103 998) is a new standard developed by the DASH Industry Forum (DASH-IF), defining means for managing DASH [5] media delivery using multiple content delivery networks (CDNs). At the server-...

Nowadays, establishing security in data transmission is essential, and it is achieved by cryptography. Encryption of still or video images in specific applications such as Internet of Things, medical and satellite imaging, in applications ...$\mathrm{}\mathrm{}$

Field-programmable gate array (FPGA)–based accelerators are becoming increasingly popular for deep neural network (DNN) inference due to their ability to scale performance with increasing degrees of specialization with dataflow architectures or custom ...

• Exploration of optimal Trojan resistant design using area-latency tradeoff.
• A novel methodology for functional Trojan-resistant hardware IP design.
• Presents low-cost optimized Trojan-resistant design using PSO-DSE.
• Attains ...

Hardware Trojans that have the capability to change the computed functional output in intellectual property (IP) cores, integrated into computing systems can be a vital reliability concern in the context of correct system operation. Therefore, ...

Cloud Warehouses have been exploiting CPU-FPGA collaborative environments, where clients share the same infrastructure to maximize resource utilization with energy efficiency. In this scope, resource provisioning is challenging as ...

Graph neural networks (GNNs) combine sparse and dense data compute requirements that are challenging to meet in resource-constrained embedded hardware. In this paper, we investigate a dataflow of dataflows architecture that optimizes data access ...

The field of computer vision is steadily growing in its complexity and application areas. FPGAs have shown that they can meet the growing demands for performance and energy efficiency. However, their programmability is a major challenge for ...

In genome analysis, it is often important to identify variants from a reference genome. However, identifying variants that occur with low frequency can be challenging, as it is computationally intensive to do so accurately. LoFreq is a widely used program ...