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- research-articleJuly 2024
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips
AbstractThe Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip's operational efficiency and overall lifespan. Most studies primarily center around performance-related ...
Highlights
- Bias Temperature Instability (BTI) aging demonstrates substantial benifits concerning spatial power density and temperature.
- Analysis leverages degradation-aware cell libraries for a 10-year aging perspective.
- A Python-based power ...
- research-articleJanuary 2023
An aging monitoring scheme for SRAM decoders
Integration, the VLSI Journal (INTG), Volume 88, Issue CPages 108–115https://doi.org/10.1016/j.vlsi.2022.09.009AbstractA major concern in modern SRAMs is the reliability degradation. The increased process variations as well as BTI or HCI phenomena are crucial factors for degrading the reliability of all SRAM blocks, such as the Address Decoders. Over-...
Highlights- SRAM Decoders suffer from aging phenomena affecting their performance.
- Aging ...
- research-articleAugust 2021
Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers
Journal of Electronic Testing: Theory and Applications (JELT), Volume 37, Issue 4Pages 533–544https://doi.org/10.1007/s10836-021-05967-9AbstractCMOS technology scaling allows the design of even more complex system but, at the same time, introduces some reliability problems. In particular, aggressively scaled microelectronic technologies are affected by the Bias Temperature Instability (...
- research-articleJune 2020
Statistical analysis of the impact of charge traps in p-type MOSFETs via particle-based Monte Carlo device simulations
Journal of Computational Electronics (SPJCE), Volume 19, Issue 2Pages 648–657https://doi.org/10.1007/s10825-020-01478-6AbstractIn this paper, statistical analysis of the static impact of charge traps on the drain current of p-type metal–oxide–semiconductor field-effect transistors is presented. The study was carried out by employing a 3-D particle-based Monte Carlo device ...
- research-articleMay 2020
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level
- P. Saraza-Canflanca,
- J. Diaz-Fortuny,
- R. Castro-Lopez,
- E. Roca,
- J. Martin-Martinez,
- R. Rodriguez,
- M. Nafria,
- F.V. Fernandez
Integration, the VLSI Journal (INTG), Volume 72, Issue CPages 13–20https://doi.org/10.1016/j.vlsi.2020.02.002AbstractIn the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot-Carrier Injection and Random Telegraph Noise can largely ...
Highlights- Complete Reliability-Aware Design flow is presented.
- It includes ...
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- review-articleMay 2020
Analysis of SRAM metrics for data dependent BTI degradation and process variability
Integration, the VLSI Journal (INTG), Volume 72, Issue CPages 148–162https://doi.org/10.1016/j.vlsi.2020.01.006AbstractBias Temperature Instability (BTI) is one of the most crucial reliability issues in modern CMOS technology. It leads to shift in device parameters, which eventually affect circuit performance. SRAM is a widely used circuit which ...
- research-articleMarch 2020
TCAD simulations and accurate extraction of reliability-aware statistical compact models
Journal of Computational Electronics (SPJCE), Volume 19, Issue 1Pages 359–366https://doi.org/10.1007/s10825-019-01428-xAbstractIn this paper, we focus on the TCAD simulation and accurate compact model extraction of the time evolution of statistical variability in conventional (bulk) CMOS transistors, due to bias temperature instability (BTI). The 25-nm physical gate ...
- research-articleFebruary 2020
Aging-mitigation of cache memories by Intra-Word Bit Swapping
Microprocessors & Microsystems (MSYS), Volume 72, Issue Chttps://doi.org/10.1016/j.micpro.2019.102941AbstractAging is one of the most crucial reliability issues in recent chip fabrication technologies. Among different causes for aging, ``Bias Temperature Instability'' (BTI) imposes the highest semiconductor degradation rate to processors. ...
- research-articleJanuary 2020
Design of BTI sensor-based improved SRAM for mobile computing applications
International Journal of Intelligent Systems Technologies and Applications (IJISTA), Volume 19, Issue 4Pages 332–347https://doi.org/10.1504/ijista.2020.110008Reliability of electronic components is the major concern as the CMOS technology is scaled down especially in mobile computing applications of MPEG video processor design. Scaling CMOS technology leads to increase in power density per unit area in an ...
- articleApril 2019
Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers
Journal of Electronic Testing: Theory and Applications (JELT), Volume 35, Issue 2Pages 261–267https://doi.org/10.1007/s10836-019-05788-xIn this paper we analyze the effect of the Bias Temperature Instability (BTI) aging phenomenon on the delay of deskew buffers employed in high performance microprocessors. Our analysis shows that, during circuit lifetime, the delay induced by BTI on ...
- research-articleJanuary 2018
Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited)
Integration, the VLSI Journal (INTG), Volume 60, Issue CPages 132–152https://doi.org/10.1016/j.vlsi.2017.08.009In this article, we will present recent advances in reliability effects such as electromigration on interconnects and Negative/Positive Bias Temperature Instability (N/P BTI) effects on CMOS devices, which are the most important reliability concerns for ...
- research-articleJune 2017
Impact of AlN layer sandwiched between the GaN and the Al2O3 layers on the performance and reliability of recessed AlGaN/GaN MOS-HEMTs
Microelectronic Engineering (MCEE), Volume 178, Issue CPages 42–47https://doi.org/10.1016/j.mee.2017.04.044This work compares the performance and the reliability of recessed-gate AlGaN/GaN MOS-HEMTs with two different gate dielectrics: a single layer of Al2O3 and a bilayer of AlN/Al2O3. Although the normally-OFF operation is well observed in the AlN/Al2O3 ...
- research-articleJanuary 2017
Implications of accelerated self-healing as a key design knob for cross-layer resilience
Integration, the VLSI Journal (INTG), Volume 56, Issue CPages 167–180https://doi.org/10.1016/j.vlsi.2016.10.008In this paper we propose a cross-layer accelerated self-healing (CLASH) system which "repairs" its wearout issues in a physical sense through accelerated and active recovery, by which wearout can be reversed while actively applying several accelerated ...
- articleMarch 2016
On the composition of ISO 25964 hierarchical relations (BTG, BTP, BTI)
International Journal on Digital Libraries (IJDL), Volume 17, Issue 1Pages 39–48https://doi.org/10.1007/s00799-015-0162-2Knowledge organization systems (KOS) can use different types of hierarchical relations: broader generic (BTG), broader partitive (BTP), and broader instantial (BTI). The latest ISO standard on thesauri (ISO 25964) has formalized these relations in a ...
- research-articleDecember 2015
Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 1Article No.: 5, Pages 1–26https://doi.org/10.1145/2783435Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to bias temperature instability and hot carrier injection. As a result, device delays increase over time, reducing the mean time to failure (MTTF) and hence ...
- research-articleNovember 2015
Extensive study of Bias Temperature Instability in nanowire transistors
Microelectronic Engineering (MCEE), Volume 147, Issue CPages 10–14https://doi.org/10.1016/j.mee.2015.04.028Display Omitted BTI Reliability in nanowire devices.NBTI vs. oxide field from CV measurement.Electrostatic simulations of several trigate devices.Dit characterization to determine sidewall influence.Gate stack influence on both PBTI and NBTI. In this ...
- research-articleAugust 2015
Optimum Operating Points of Transistors with minimal Aging-Aware Sensitivity
SBCCI '15: Proceedings of the 28th Symposium on Integrated Circuits and Systems DesignArticle No.: 14, Pages 1–7https://doi.org/10.1145/2800986.2801021Degradation of the threshold voltage in CMOS transistors affects the performance of analog circuits over time. In order to meet set target specifications, the influence of these degradation modes needs to be considered and compensated during the design ...
- research-articleMarch 2015
Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI
DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & ExhibitionPages 441–446Aging induced degradation mechanisms occurring in digital circuits are of a greater importance in the latest technologies. Monotonic degradation such as Bias Temperature Instability (BTI) or Hot Carrier Injection (HCI) but also sudden degradation such ...
- research-articleJune 2014
Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques
DAC '14: Proceedings of the 51st Annual Design Automation ConferencePages 1–6https://doi.org/10.1145/2593069.2593162In this paper we postulate that future electronics systems will use sleep time as an active recovery period essential for their overall performance. Our hypothesis is that by explicitly controlling the ratio of sleep vs. active and sleep conditions (...
- research-articleJune 2014
CACI: Dynamic Current Analysis Towards Robust Recycled Chip Identification
DAC '14: Proceedings of the 51st Annual Design Automation ConferencePages 1–6https://doi.org/10.1145/2593069.2593102Rising incidences of counterfeit chips in the supply chain have posed a serious threat to the semiconductor industry. Recycling of used chips constitutes a major form of counterfeiting attacks. If undetected, they can lead to serious consequences ...