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An experimental distributed switching system to handle bursty computer traffic

Published: 13 October 1969 Publication History

Abstract

An experimental switching system has been built using commercially available integrated semiconductors to switch data. Data messages to be handled by the system may vary in bit rate (100 bits/sec - 4 × 106 bits/sec), message length, and rate of message occurrence.
The system uses a synchronous transmission facility with a crystal stabilized clock rate of approximately 6 MHz. The signaling format chosen facilitates data interchange between a number of similar small sequential machines that share a common transmission facility. Efficient data transmission over common carrier systems requires a change in signal format at the channel inputs.
Systems involving interconnected loops are discussed briefly; however, the traffic handling capacity of such systems must be analyzed to determine the memory requirements at the junction points. This paper is concerned primarily with the detailed organization of a single loop.

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cover image ACM Conferences
Proceedings of the first ACM symposium on Problems in the optimization of data communications systems
October 1969
421 pages
ISBN:9781450374743
DOI:10.1145/800165
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 October 1969

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