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Exploring DNA Alignment-in-Memory Leveraging Emerging SOT-MRAM

Published: 07 September 2020 Publication History

Abstract

In this work, we review two alternative Processing-in-Memory (PIM) accelerators based on Spin-Orbit-Torque Magnetic Random Access Memory (SOT-MRAM) to execute DNA short read alignment based on an optimized and hardware-friendly alignment algorithm. We first discuss the reconstruction of the existing sequence alignment algorithm based on BWT and FM-index such that it can be fully implemented leveraging PIM functions. We then transform SOT-MRAM array to a potential computational memory by presenting two different reconfigurable sense amplifiers to accelerate the reconstructed alignment-in-memory algorithm. The cross-layer simulation results show that such PIM platforms are able to achieve a nearly ten-fold and two-fold increases in throughput/power/area measure compared with recent ASIC and processing-in-ReRAM designs, respectively.

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References

[1]
H. Li and N. Homer, "A survey of sequence alignment algorithms for next-generation sequencing," Briefings in bioinformatics, vol. 11, no. 5, pp. 473--483, 2010.
[2]
H. Li and R. Durbin, "Fast and accurate short read alignment with burrows--wheeler transform," bioinformatics, vol. 25, pp. 1754--1760, 2009.
[3]
F. Zokaee et al., "Aligner: A process-in-memory architecture for short read alignment in rerams," IEEE Computer Architecture Letters, 2018.
[4]
B. Langmead et al., "Ultrafast and memory-efficient alignment of short dna sequences to the human genome," Genome biology, vol. 10, p. R25, 2009.
[5]
R. Luo et al., "Soap3-dp: fast, accurate and sensitive gpu-based short read aligner," PloS one, vol. 8, p. e65632, 2013.
[6]
A. Madhavan et al., "Race logic: A hardware acceleration for dynamic programming algorithms," in ACM SIGARCH Computer Architecture News, vol. 42, 2014.
[7]
Y. Turakhia et al., "Darwin: A genomics co-processor provides up to 15,000 x acceleration on long read assembly," in 23rd ASPLOS. hskip 1em plus 0.5em minus 0.4emrelax ACM, 2018, pp. 199--213.
[8]
Y.-C. Wu et al., "A 135-mw fully integrated data processor for next-generation sequencing," IEEE TBioCAS, vol. 11, pp. 1216--1225, 2017.
[9]
J. Arram et al., "Leveraging fpgas for accelerating short read alignment," IEEE/ACM TCBB, vol. 14, pp. 668--677, 2017.
[10]
S. Angizi and D. Fan, "Redram: A reconfigurable processing-in-dram platform for accelerating bulk bit-wise operations," in 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). hskip 1em plus 0.5em minus 0.4emrelax IEEE, 2019, pp. 1--8.
[11]
S. Angizi, Z. He, F. Parveen, and D. Fan, "Rimpa: A new reconfigurable dual-mode in-memory processing architecture with spin hall effect-driven domain wall motion device," in 2017 IEEE Computer Society annual symposium on VLSI (ISVLSI). hskip 1em plus 0.5em minus 0.4emrelax IEEE, 2017, pp. 45--50.
[12]
W. Huangfu et al., "Radar: a 3d-reram based dna alignment accelerator architecture," in 55th DAC. hskip 1em plus 0.5em minus 0.4emrelax ACM, 2018, p. 59.
[13]
S. Angizi and D. Fan, "Accelerating bulk bit-wise x (n) or operation in processing-in-dram platform," arXiv preprint arXiv:1904.05782, 2019.
[14]
S. K. Khatamifard et al., "A non-volatile near-memory read mapping accelerator," arXiv preprint arXiv:1709.02381, 2017.
[15]
L. Yavits et al., "Resistive associative processor," IEEE Computer Architecture Letters, vol. 14, pp. 148--151, 2015.
[16]
S. Angizi, J. Sun, W. Zhang, and D. Fan, "Aligns: A processing-in-memory accelerator for dna short read alignment leveraging sot-mram," in 2019 56th ACM/IEEE Design Automation Conference (DAC). hskip 1em plus 0.5em minus 0.4emrelax IEEE, 2019, pp. 1--6.
[17]
Z. I. Chowdhury, M. Zabihi, S. K. Khatamifard, Z. Zhao, S. Resch, M. Razaviyayn, J.-P. Wang, S. S. Sapatnekar, and U. R. Karpuzcu, "A dna read alignment accelerator based on computational ram," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2020.
[18]
S. Angizi, Z. He, and D. Fan, "Dima: a depthwise cnn in-memory accelerator," in 2018 ICCAD. hskip 1em plus 0.5em minus 0.4emrelax IEEE, 2018, pp. 1--8.
[19]
S. Angizi, Z. He, A. S. Rakin, and D. Fan, "Cmp-pim: an energy-efficient comparator-based processing-in-memory neural network accelerator," in Proceedings of the 55th Annual Design Automation Conference. hskip 1em plus 0.5em minus 0.4emrelax ACM, 2018, p. 105.
[20]
S. Angizi, Z. He, F. Parveen, and D. Fan, "Imce: Energy-efficient bit-wise in-memory convolution engine for deep neural network," in 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC). hskip 1em plus 0.5em minus 0.4emrelax IEEE, 2018, pp. 111--116.
[21]
S. Angizi, J. Sun, W. Zhang, and D. Fan, "Pim-aligner: A processing-in-mram platform for biological sequence alignment," in 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). hskip 1em plus 0.5em minus 0.4emrelax IEEE, 2020, pp. 1265--1270.
[22]
S. Canzar et al., "Short read mapping: An algorithmic tour," Proceedings of the IEEE, pp. 436--458, 2017.
[23]
S. Angizi and D. Fan, "Graphide: A graph processing accelerator leveraging in-dram-computing," in Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019, pp. 45--50.
[24]
X. Fong, Y. Kim, K. Yogendra, D. Fan, A. Sengupta, A. Raghunathan, and K. Roy, "Spin-transfer torque devices for logic and memory: Prospects and perspectives," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 1, pp. 1--22, 2015.
[25]
S. Angizi, Z. He, A. Awad, and D. Fan, "Mrima: An mram-based in-memory accelerator," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 5, pp. 1123--1136, 2019.
[26]
S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, "Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories," in Proceedings of the 53rd Annual Design Automation Conference, 2016, pp. 1--6.
[27]
S. V. Kosonocky et al., "Enchanced multi-threshold (mtcmos) circuits using variable well bias," in ISLPED, 2001, pp. 165--169.
[28]
H. Ozdemir, A. Kepkep, B. Pamir, Y. Leblebici, and U. Cilingiroglu, "A capacitive threshold-logic gate," IEEE Journal of Solid-State Circuits, vol. 31, no. 8, pp. 1141--1150, 1996.
[29]
X. Dong et al., "Nvsim: A circuit-level performance, energy, and area model for emerging non-volatile memory," in Emerging Memory Technologies. hskip 1em plus 0.5em minus 0.4emrelax Springer, 2014, pp. 15--50.
[30]
R. Kaplan et al., "A resistive cam processing-in-storage architecture for dna sequence alignment," IEEE Micro, vol. 37, pp. 20--28, 2017.
[31]
W. Huang et al., "Art: a next-generation sequencing read simulator," Bioinformatics, vol. 28, pp. 593--594, 2011.

Cited By

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  • (2024)HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With an Offset-Compensated Comparator2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528704(1-7)Online publication date: 3-Apr-2024
  • (2023)Aligner-D: Leveraging In-DRAM Computing to Accelerate DNA Short Read AlignmentIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.324154513:1(332-343)Online publication date: Mar-2023
  • (2023)Invited: Accelerating Genome Analysis via Algorithm-Architecture Co-Design2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247887(1-4)Online publication date: 9-Jul-2023
  • Show More Cited By

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cover image ACM Other conferences
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI
September 2020
597 pages
ISBN:9781450379441
DOI:10.1145/3386263
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 September 2020

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Author Tags

  1. DNA alignment
  2. bioinformatics
  3. processing-in-memory

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  • Research-article

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  • National Science Foundation

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GLSVLSI '20
GLSVLSI '20: Great Lakes Symposium on VLSI 2020
September 7 - 9, 2020
Virtual Event, China

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2024)HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With an Offset-Compensated Comparator2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528704(1-7)Online publication date: 3-Apr-2024
  • (2023)Aligner-D: Leveraging In-DRAM Computing to Accelerate DNA Short Read AlignmentIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.324154513:1(332-343)Online publication date: Mar-2023
  • (2023)Invited: Accelerating Genome Analysis via Algorithm-Architecture Co-Design2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247887(1-4)Online publication date: 9-Jul-2023
  • (2022)pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00067(900-919)Online publication date: Oct-2022
  • (2022)Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI54635.2022.00060(273-278)Online publication date: Jul-2022
  • (2022)Emerging Memory Structures for VLSI CircuitsWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W8438(1-28)Online publication date: 12-May-2022

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