Session details: Novel techniques to minimize circuit failure
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Circuit-level techniques to control gate leakage for sub-100nm CMOS
ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and designAlthough still negligible for state-of-the-art CMOS, gate leakage will become significant in the future for sub-100nm technologies, due to the scaling of oxide thickness. We propose several circuit techniques to control gate leakage based on the fact ...
Session details: Oral Session 3: Multimedia Applications (Oral presentations)
ICMR '17: Proceedings of the 2017 ACM on International Conference on Multimedia RetrievalLeakage power and circuit aging cooptimization by gate replacement techniques
As technology scales, the aging effect caused by negative bias temperature instability (NBTI) has become a major reliability concern. In the mean time, reducing leakage power remains to be one of the key design goals. Because both NBTI-induced circuit ...
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- EDAC: Electronic Design Automation Consortium
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE-CAS: Circuits & Systems
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Association for Computing Machinery
New York, NY, United States
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