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Adaptive software cache management for distributed shared memory architectures

Authors:

John K. Bennett,

John B. Carter,

Willy ZwaenepoelAuthors Info & Claims

ISCA '90: Proceedings of the 17th annual international symposium on Computer Architecture

Pages 125 - 134

https://doi.org/10.1145/325164.325124

Published: 01 May 1990 Publication History

Abstract

An adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. We contend that, in distributed shared memory systems, adaptive cache coherence mechanisms will outperform static cache coherence mechanisms. We have examined the sharing and synchronization behavior of a variety of shared memory parallel programs. We have found that the access patterns of a large percentage of shared data objects fall in a small number of categories for which efficient software coherence mechanisms exist. In addition, we have performed a simulation study that provides two examples of how an adaptive caching mechanism can take advantage of semantic information.

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Cited By

Fraguela BAndrade D(2021)A software cache autotuning strategy for dataflow computing with UPC++ DepSpawnComputational and Mathematical Methods10.1002/cmm4.1148Online publication date: 22-Feb-2021
https://doi.org/10.1002/cmm4.1148
Shield JDiguet JGogniat G(2012)Asymmetric Cache CoherencyACM Transactions on Reconfigurable Technology and Systems10.1145/2362374.23623765:3(1-12)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1145/2362374.2362376
Barrow-Williams NFensch CMoore S(2009)A communication characterisation of Splash-2 and ParsecProceedings of the 2009 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2009.5306792(86-97)Online publication date: 4-Oct-2009
https://dl.acm.org/doi/10.1109/IISWC.2009.5306792
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Index Terms

Adaptive software cache management for distributed shared memory architectures
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM Conferences

ISCA '90: Proceedings of the 17th annual international symposium on Computer Architecture

May 1990

378 pages

ISBN:0897913663

DOI:10.1145/325164

ACM SIGARCH Computer Architecture News Volume 18, Issue 2SI
Special Issue: Proceedings of the 17th annual international symposium on Computer Architecture
June 1990
356 pages
ISSN:0163-5964
DOI:10.1145/325096
Chairmen:
Jean-Loup Baer,
Larry Snyder,
James Goodman
Issue’s Table of Contents

Copyright © 1990 Authors.

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SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1990

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ISCA90

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ISCA90: International Symposium on Computer Architecture

May 28 - 31, 1990

Washington, Seattle, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Citations

Cited By

Fraguela BAndrade D(2021)A software cache autotuning strategy for dataflow computing with UPC++ DepSpawnComputational and Mathematical Methods10.1002/cmm4.1148Online publication date: 22-Feb-2021
Shield JDiguet JGogniat G(2012)Asymmetric Cache CoherencyACM Transactions on Reconfigurable Technology and Systems10.1145/2362374.23623765:3(1-12)Online publication date: 1-Oct-2012
Barrow-Williams NFensch CMoore S(2009)A communication characterisation of Splash-2 and ParsecProceedings of the 2009 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2009.5306792(86-97)Online publication date: 4-Oct-2009
Jacob BNg SWang D(2007)Memory SystemsundefinedOnline publication date: 10-Sep-2007
Manson JPugh WAdve S(2005)The Java memory modelACM SIGPLAN Notices10.1145/1047659.104033640:1(378-391)Online publication date: 12-Jan-2005
Manson JPugh WAdve SPalsberg JAbadi M(2005)The Java memory modelProceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages10.1145/1040305.1040336(378-391)Online publication date: 12-Jan-2005
Sarojadevi HNandy SBalakrishnan S(2004)On the correctness of program execution when cache coherence is maintained locally at data-sharing boundaries in distributed shared memory multiprocessorsInternational Journal of Parallel Programming10.1023/B:IJPP.0000038070.79088.0b32:5(415-446)Online publication date: 1-Oct-2004
Udayakumaran SBarua RMoreno JMurthy PConte TFaraboschi P(2003)Compiler-decided dynamic memory allocation for scratch-pad based embedded systemsProceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems10.1145/951710.951747(276-286)Online publication date: 30-Oct-2003
Martin MHarper PSorin DHill MWood D(2003)Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessorsACM SIGARCH Computer Architecture News10.1145/871656.85964231:2(206-217)Online publication date: 1-May-2003
Martin MHarper PSorin DHill MWood DGottlieb ALi K(2003)Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessorsProceedings of the 30th annual international symposium on Computer architecture10.1145/859618.859642(206-217)Online publication date: 9-Jun-2003
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