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dRMT: Disaggregated Programmable Switching

Authors:

Andy Fingerhut,

Anirudh Sivaraman,

Shay Vargaftik,

Mohammad Alizadeh,

Shang-Tse Chuang,

Isaac Keslassy,

Tom EdsallAuthors Info & Claims

SIGCOMM '17: Proceedings of the Conference of the ACM Special Interest Group on Data Communication

Pages 1 - 14

https://doi.org/10.1145/3098822.3098823

Published: 07 August 2017 Publication History

Abstract

We present dRMT (disaggregated Reconfigurable Match-Action Table), a new architecture for programmable switches. dRMT overcomes two important restrictions of RMT, the predominant pipeline-based architecture for programmable switches: (1) table memory is local to an RMT pipeline stage, implying that memory not used by one stage cannot be reclaimed by another, and (2) RMT is hardwired to always sequentially execute matches followed by actions as packets traverse pipeline stages. We show that these restrictions make it difficult to execute programs efficiently on RMT.

dRMT resolves both issues by disaggregating the memory and compute resources of a programmable switch. Specifically, dRMT moves table memories out of pipeline stages and into a centralized pool that is accessible through a crossbar. In addition, dRMT replaces RMT's pipeline stages with a cluster of processors that can execute match and action operations in any order.

We show how to schedule a P4 program on dRMT at compile time to guarantee deterministic throughput and latency. We also present a hardware design for dRMT and analyze its feasibility and chip area. Our results show that dRMT can run programs at line rate with fewer processors compared to RMT, and avoids performance cliffs when there are not enough processors to run a program at line rate. dRMT's hardware design incurs a modest increase in chip area relative to RMT, mainly due to the crossbar.

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Cited By

Song XLu RGuo Z(2024)High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNICMicromachines10.3390/mi1504044915:4(449)Online publication date: 27-Mar-2024
https://doi.org/10.3390/mi15040449
Lerner AZoni DCosta PAntichi G(2024)Rethinking the Switch Architecture for Stateful In-network ComputingProceedings of the 23rd ACM Workshop on Hot Topics in Networks10.1145/3696348.3696897(273-281)Online publication date: 18-Nov-2024
https://dl.acm.org/doi/10.1145/3696348.3696897
Mittal SV. HHeetkumar PTammana PGopalakrishnan VWang JAyyub Qazi ITyson G(2024)iGuard: Efficient Isolation Forest Design for Malicious Traffic Detection in Programmable SwitchesProceedings of the 20th International Conference on emerging Networking EXperiments and Technologies10.1145/3680121.3697807(55-64)Online publication date: 9-Dec-2024
https://dl.acm.org/doi/10.1145/3680121.3697807
Show More Cited By

Index Terms

dRMT: Disaggregated Programmable Switching
1. Networks
  1. Network components
    1. Intermediate nodes
      1. Bridges and switches
  2. Network services
    1. Programmable networks

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Published In

cover image ACM Conferences

SIGCOMM '17: Proceedings of the Conference of the ACM Special Interest Group on Data Communication

August 2017

515 pages

ISBN:9781450346535

DOI:10.1145/3098822

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Publication History

Published: 07 August 2017

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Research-article
Research
Refereed limited

Funding Sources

Hasso Plattner Institute Research School
National Science Foundation
Cisco Research Center
Ministry of Science and Technology, Israel
Shillman Fund for Global Security
Gordon Fund for Systems Engineering
Technion Fund for Security Research
Israeli Consortium for Network Programming

Conference

SIGCOMM '17

Sponsor:

SIGCOMM

SIGCOMM '17: ACM SIGCOMM 2017 Conference

August 21 - 25, 2017

CA, Los Angeles, USA

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Overall Acceptance Rate 462 of 3,389 submissions, 14%

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Cited By

Song XLu RGuo Z(2024)High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNICMicromachines10.3390/mi1504044915:4(449)Online publication date: 27-Mar-2024
https://doi.org/10.3390/mi15040449
Lerner AZoni DCosta PAntichi G(2024)Rethinking the Switch Architecture for Stateful In-network ComputingProceedings of the 23rd ACM Workshop on Hot Topics in Networks10.1145/3696348.3696897(273-281)Online publication date: 18-Nov-2024
https://dl.acm.org/doi/10.1145/3696348.3696897
Mittal SV. HHeetkumar PTammana PGopalakrishnan VWang JAyyub Qazi ITyson G(2024)iGuard: Efficient Isolation Forest Design for Malicious Traffic Detection in Programmable SwitchesProceedings of the 20th International Conference on emerging Networking EXperiments and Technologies10.1145/3680121.3697807(55-64)Online publication date: 9-Dec-2024
https://dl.acm.org/doi/10.1145/3680121.3697807
Yang YHe LZhou JShi XCao JLiu YSekar VYu MSeneviratne AVeitch D(2024)P4runpro: Enabling Runtime Programmability for RMT Programmable SwitchesProceedings of the ACM SIGCOMM 2024 Conference10.1145/3651890.3672230(921-937)Online publication date: 4-Aug-2024
https://dl.acm.org/doi/10.1145/3651890.3672230
Chen ZFeng YLiu SSong HZhou HYun TXu WPan TLiu BSekar VYu MSeneviratne AVeitch D(2024)OptimusPrime: Unleash Dataplane Programmability through a Transformable ArchitectureProceedings of the ACM SIGCOMM 2024 Conference10.1145/3651890.3672214(904-920)Online publication date: 4-Aug-2024
https://dl.acm.org/doi/10.1145/3651890.3672214
Song XGuo Z(2024)An Implementation of Reconfigurable Match Table for FPGA-Based Programmable SwitchesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.343604732:11(2121-2134)Online publication date: Nov-2024
https://doi.org/10.1109/TVLSI.2024.3436047
Vass BBérczi-Kovács EFraknói ÁRaiciu CRétvári G(2024)Charting the Complexity Landscape of Compiling Packet Programs to Reconfigurable SwitchesIEEE/ACM Transactions on Networking10.1109/TNET.2024.342433732:5(4519-4534)Online publication date: Oct-2024
https://doi.org/10.1109/TNET.2024.3424337
Chen XZhang WSun XLiu HZhang JHuang QZhang DZhou HLiu XWu C(2024)Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable SwitchesIEEE/ACM Transactions on Networking10.1109/TNET.2024.341353032:5(4191-4206)Online publication date: Oct-2024
https://doi.org/10.1109/TNET.2024.3413530
Chen XLiu HXiao QHuang QZhang DZhou HZhou BWu CLiu XYang Q(2024)Hermes: Low-Overhead Inter-Switch Coordination in Network-Wide Data Plane Program DeploymentIEEE/ACM Transactions on Networking10.1109/TNET.2024.336132432:4(2842-2857)Online publication date: Aug-2024
https://doi.org/10.1109/TNET.2024.3361324
Iliadis-Apostolidis DManaa KKadosh MIoannou IVassiliou VKosta SVegas Olmos J(2024)Towards Accelerating the Network Performance on DPUs by optimising the P4 runtime2024 32nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP62718.2024.00040(238-244)Online publication date: 20-Mar-2024
https://doi.org/10.1109/PDP62718.2024.00040
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