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Efficient switching activity simulation under a real delay model using a bitparallel approach

Authors:

M. Bühler,

M. Papesch,

K. Kapp,

U. G. BaitingerAuthors Info & Claims

DATE '99: Proceedings of the conference on Design, automation and test in Europe

Pages 96 - es

https://doi.org/10.1145/307418.307544

Published: 01 January 1999 Publication History

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References

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{1} Monteiro et al., Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 1, January 1997, pp. 121-127.

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{2} Najm F., Transition Density: A New Measure of Activity in Digital Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 2, February 1992, pp. 310-323.

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{3} P.H. Schneider, PAPSAS: A Fast Switching Activity Simulator , PATMOS'95, 1995, pp. 351-360.

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{6} M. Bühler, D. Dallmann, U. G. Baitinger, Switching Activity Analysis Using a Set Theoretical Approach, GI/ITG/ GME Workshop 1998, Paderborn, ISBN 3-931466-35-3.

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{7} Marculescu R., Marculescu D., Pedram M., Efficient Power Estimation for Highly Correlated Input Streams, 32nd Design Automation Conference DAC, 1995, pp. 628-634.

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{8} Chou T., Roy K., Prasad S., Estimation of Circuit Activity Considering Signal Correlations and Simultaneous Switching, IEEE/ACM International Conference on CAD- 94, 1994, pp. 300-303.

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{9} Kapp K., Bühler M., Dallmann D., Baitinger U.G., TESA: Timeparallel Estimation of Switching Activity under a Real Delay Model, ICECS'98, Lisbon, Portugal, 1998.

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{10} Chou T., Roy K., Prasad S., Estimation of Circuit Activity Considering Signal Correlations and Simultaneous Switching, IEEE/ACM International Conference on CAD- 94, 1994, pp. 300-303.

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Cited By

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Alishzadeh YJassbi SReshadi M(2023)Energy management of fault-tolerant real-time embedded systems through switching-activity-based techniquesMicroprocessors and Microsystems10.1016/j.micpro.2023.104929102(104929)Online publication date: Oct-2023
https://doi.org/10.1016/j.micpro.2023.104929
Murugavel ARanganathan N(2003)Petri net modeling of gate and interconnect delays for power estimationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81711011:5(921-927)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.817110
Becker JHuebner MUllmann M(2003)Power estimation and power measurement of Xilinx Virtex FPGAs: trade-offs and limitations16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.10.1109/SBCCI.2003.1232842(283-288)Online publication date: 2003
https://doi.org/10.1109/SBCCI.2003.1232842
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Index Terms

Efficient switching activity simulation under a real delay model using a bitparallel approach
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Digital switches
      1. Logic families

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DATE '99: Proceedings of the conference on Design, automation and test in Europe

January 1999

730 pages

ISBN:1581131216

DOI:10.1145/307418

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1999

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Cited By

View all

Alishzadeh YJassbi SReshadi M(2023)Energy management of fault-tolerant real-time embedded systems through switching-activity-based techniquesMicroprocessors and Microsystems10.1016/j.micpro.2023.104929102(104929)Online publication date: Oct-2023
https://doi.org/10.1016/j.micpro.2023.104929
Murugavel ARanganathan N(2003)Petri net modeling of gate and interconnect delays for power estimationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81711011:5(921-927)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.817110
Becker JHuebner MUllmann M(2003)Power estimation and power measurement of Xilinx Virtex FPGAs: trade-offs and limitations16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.10.1109/SBCCI.2003.1232842(283-288)Online publication date: 2003
https://doi.org/10.1109/SBCCI.2003.1232842
Murugavel ARanganathan N(2002)A Real Delay Switching Activity Simulator based on Petri net ModelingProceedings of the 2002 Asia and South Pacific Design Automation Conference10.5555/832284.835485Online publication date: 7-Jan-2002
https://dl.acm.org/doi/10.5555/832284.835485
Murugavel ARanganathan NAckland B(2002)Petri net modeling of gate and interconnect delays for power estimationProceedings of the 39th annual Design Automation Conference10.1145/513918.514034(455-460)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.514034

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Statistical gate delay model for multiple input switching

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Hybrid Model Using Interacted-ARIMA and ANN Models for Efficient Forecasting