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C Compiler Design for an Industrial Network Processor

Published: 01 August 2001 Publication History

Abstract

One important problem in code generation for embedded processors is the design of efficient compilers for ASIPs with application specific architectures. This paper outlines the design of a C compiler for an industrial ASIP for telecom applications. The target ASIP is a network processor with special instructions for bit-level access to data registers, which is required for packet-oriented communication protocol processing. From a practical viewpoint, we describe the main challenges in exploiting these application specific features in a C compiler, and we show how a compiler backend has been designed that accomodates these features by means of compiler intrinsics and a dedicated register allocator. The compiler is fully operational, and first experimental results indicate that C-level programming of the ASIP leads to good code quality without the need for time-consuming assembly programming.

References

[1]
Tensilica Inc.: www.tensilica.com]]
[2]
Austria Mikro Systeme International: asic.a msint.com/data books/digital/gepa rd.html, 2000]]
[3]
B. Wess: Automatic Instruction Code Generation based on Trellis Diagrams, IEEE Int. Syrup. on Circuits and Systems (ISCAS), 1992]]
[4]
G. Araujo, S. Malik: Optimal Code Generation for Embedded Memory Non-Homogeneous Register Arehitectures, 8th Int. Syrup. on System Synthesis (isss), 1995]]
[5]
S. Liao, S. Devadas, K. Kentzer, S. Tjiang, A. Wang: Code Optimization Techniques for Embedded DSP Microprocessors, 32nd Design Automation Conference (DAC), 1995]]
[6]
A. Timmer, M. Strik, J. van Meerbergen, J. Jess: Conflict Modeling and Instruction Scheduling in Code Generation for In-House DSP Cores, 32nd Design Automation Conference (DAC), 1995]]
[7]
S. Bashford, R. Leupers: Constraint Driven Code Selection for Fixed-Point DSPs, 36th Design Automation Conference (DAC), 1999]]
[8]
D.H. Bartley: Optimizing Stack Frame Accesses for Processors with Restricted Addressing Modes, Software Practice and Experience, vol. 22(2), 1992]]
[9]
S. Liao, S. Devadas, K. Keutzer, S. Tjiang, A. Wang: Storage Assignment to Decrease Code Size, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1995]]
[10]
R. Leupers, F. David: A Uniform Optimization Technique for Offset Assignment Problems, llth Int. System Synthesis Symposium (ISSS), 1998]]
[11]
E. Eckstein, A. Kralh Minimizing Cost of Local Variables Access for DSP Processors, ACM Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES), 1999]]
[12]
R.J. Fisher, H.G. Dietz: Compiling for SIMD Within a Register, llth Annual Workshop on Languages and Compilers for Parallel Computing (LCPC98), 1998]]
[13]
R. Leupers: Code Selection for Media Processors with SIMD Instructions, Design Automation & Test in Europe (DATE), 2000]]
[14]
Exploiting Superword Level Parallelism with Multimedia Instruction Sets, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2000]]
[15]
Network Processors: A Perspective on Market Requirements, Processors Architectures, and Embedded S/W Tools: Design Automation & Test in Europe (DATE), 2001]]
[16]
D. Brooks, M. Martonosi: Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance HPCA-5, January 1999. Princeton University]]
[17]
M. Budiu, M. Sakr, K. Walker, S. C. Goldstein: Bit Value Inference: Detecting and Exploiting Narrow Bitwidth Computations, European Conference on Parallel Processing 2000]]
[18]
M. Stephenson, J. Babb, S. Amarasinghe: Bitwidth Analysis with Application to Silicon Compilation, Proceedings of the SIGPLAN,00, Conference on Program Language Design and Implementation, Vancouver, Canada, June 2000]]
[19]
S.C. Goldstein, H. Schmidt, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, R. Laufer: PipeRench: A Coprocessor for Streaming multimedia Acceleration, ISCA, 1999]]
[20]
S.C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R.R. Taylor: PipeRench: A Reconfigurable Architecture and Compiler, IEEE Computer, vol. 33, no. 4, pg.70-77, 2000]]
[21]
X. Nie, L. Gazsi, F. Engel, G. Fettweis: A New Network Processor Architecture for High-Speed Communications, IEEE Workshop on Signal Processing Systems (SIPS), 1999]]
[22]
C. Liem: Retar9etable Compilers for Embedded Core Processors, Kluwer Academic Publishers, 1997]]
[23]
A. Inoue, H. Tomiyama, H. Okuma, H. Kanbara, and H. Yasuura: Language and Compiler for Optimizing Datapath Widths of Embedded Systems, IEICE Trans. Fundamentals, vol. ES1-A, no. 12, pp. 2595-2604, Dec. 1998]]
[24]
A.V. Aho, M. Ganapathi, S.W.K Tjiang: Code Generation Usin9 Tree Matchin9 and Dynamic Pro9rammin9, ACM Trans. on Programming Languages and Systems 11, No. 4, 1989]]
[25]
C.W. Fraser, D.R. Hanson, T.A. Proebsting: En9ineerin9 a Simple, Efficient Code Generator Generator, ACM Letters on Programming Languages and Systems, vol. 1, no. 3, 1992]]
[26]
A. Sudarsanam: Code Optimization Libraries for Retar9etable Compilation for Embedded Digital Signal Processors, Ph.D. thesis, Princeton University, Department of Electrical Engineering, 1998]]
[27]
P. Briggs: Register Allocation via Graph Colorin9, Doctoral thesis, Dept. of Computer Science, Rice University, Houston/Texas, 1992]]
[28]
R. Leupers: Code Optimization Techniques for Embedded Processors, Kluwer Academic Publishers, 2000. URL: kS12-www.cs.uni-dortmund.de/,leupers]]
[29]
A.V. Aho, R. Sethi, J.D. Ullman: Compilers - Principles, Techniques, and Tools, Addison-Wesley, 1986]]
[30]
Free Software Foundation: www.gnu.org]]
[31]
The Stanford Compiler Group: suif.stanford.edu]]
[32]
C. Fraser, D. Hanson: A Retar9etable C Compiler: Design And Implementation, Addison-Wesley, 1995, www.cs.princeton.edu/software/Icc]]
[33]
V. Zivojnovic, J.M. Velarde, C. Schl,iger, H. Meyr: DSPStone - A DSP-oriented Benchmarking Methodology, Int. Conf. on Signal Processing Applications and Technology (ICSPAT), 1994]]
[34]
D. Callahan, S. Carr, K. Kennedy: Improving Register Allocation for Subscripted Variables, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1990]]

Cited By

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  • (2021)Fine-grained pipeline parallelization for network function programsProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370309(162-173)Online publication date: 27-Feb-2021
  • (2006)A General Development Methodology for Network Protocol Based on Network Processor2006 First International Conference on Communications and Networking in China10.1109/CHINACOM.2006.344660(1-4)Online publication date: Oct-2006
  • (2004)Towards a generic programming model for network processorsProceedings. 2004 12th IEEE International Conference on Networks (ICON 2004) (IEEE Cat. No.04EX955)10.1109/ICON.2004.1409218(504-510)Online publication date: 2004

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    cover image ACM Conferences
    OM '01: Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
    August 2001
    250 pages
    ISBN:1581134266
    DOI:10.1145/384198
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 01 August 2001

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    Author Tags

    1. compilers
    2. embedded processors
    3. network processors

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    View all
    • (2021)Fine-grained pipeline parallelization for network function programsProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370309(162-173)Online publication date: 27-Feb-2021
    • (2006)A General Development Methodology for Network Protocol Based on Network Processor2006 First International Conference on Communications and Networking in China10.1109/CHINACOM.2006.344660(1-4)Online publication date: Oct-2006
    • (2004)Towards a generic programming model for network processorsProceedings. 2004 12th IEEE International Conference on Networks (ICON 2004) (IEEE Cat. No.04EX955)10.1109/ICON.2004.1409218(504-510)Online publication date: 2004

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