research-article

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor

Authors:

Charles Meissner,

John SchumannAuthors Info & Claims

DAC '11: Proceedings of the 48th Design Automation Conference

Pages 569 - 574

https://doi.org/10.1145/2024724.2024856

Published: 05 June 2011 Publication History

Abstract

The growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification plan. It continues with common verification goals and shared tools and techniques. This paper describes our experience in improving this synergy in the pre- and post-silicon verification of IBM's POWER7 processor chip and by leveraging pre-silicon methodologies and techniques in the post-silicon validation of the chip.

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Cited By

Witharana HSanjaya SMishra P(2023)Dynamic Refinement of Hardware Assertion Checkers2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137306(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137306
Jindal NPanda PSarangi S(2018)Reusing Trace Buffers as Victim CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.282792826:9(1699-1712)Online publication date: Sep-2018
https://doi.org/10.1109/TVLSI.2018.2827928
Jayaraman PParthasarathi R(2017)A Survey on Post-Silicon Functional Validation for Multicore ArchitecturesACM Computing Surveys10.1145/310761550:4(1-30)Online publication date: 25-Aug-2017
https://dl.acm.org/doi/10.1145/3107615
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Index Terms

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
1. Hardware
  1. Hardware validation
    1. Functional verification

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Information

Published In

cover image ACM Conferences

DAC '11: Proceedings of the 48th Design Automation Conference

June 2011

1055 pages

ISBN:9781450306362

DOI:10.1145/2024724

General Chair:
Leon Stok
IBM Corp., Hopewell Jct., NY
,
Program Chairs:
Nikil Dutt
Univ. of California, Irvine, CA
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2011 Authors.

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2011

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DAC '11

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DAC '11: The 48th Annual Design Automation Conference 2011

June 5 - 10, 2011

California, San Diego

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Witharana HSanjaya SMishra P(2023)Dynamic Refinement of Hardware Assertion Checkers2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137306(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137306
Jindal NPanda PSarangi S(2018)Reusing Trace Buffers as Victim CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.282792826:9(1699-1712)Online publication date: Sep-2018
https://doi.org/10.1109/TVLSI.2018.2827928
Jayaraman PParthasarathi R(2017)A Survey on Post-Silicon Functional Validation for Multicore ArchitecturesACM Computing Surveys10.1145/310761550:4(1-30)Online publication date: 25-Aug-2017
https://dl.acm.org/doi/10.1145/3107615
Taatizadeh PNicolici N(2017)Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon ValidationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.265856425:6(1866-1880)Online publication date: Jun-2017
https://doi.org/10.1109/TVLSI.2017.2658564
Chandran SPanda PSarangi SBhattacharyya AChauhan DKumar S(2017)Managing Trace Summaries to Minimize Stalls During Postsilicon ValidationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.265760425:6(1881-1894)Online publication date: Jun-2017
https://doi.org/10.1109/TVLSI.2017.2657604
Taatizadeh PNicolici N(2016)Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon ValidationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.253808735:12(2118-2130)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TCAD.2016.2538087
Chandran SPanda PChauhan DKumar SSarangi S(2016)Extending trace history through tapered summaries in post-silicon validation2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428099(737-742)Online publication date: Jan-2016
https://doi.org/10.1109/ASPDAC.2016.7428099
Taatizadeh PNicolici NNebel WAtienza D(2015)A methodology for automated design of embedded bit-flips detectors in post-silicon validationProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755770(73-78)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755770
Taatizadeh PNicolici N(2015)Emulation-based selection and assessment of assertion checkers for post-silicon validationProceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2015.7357083(46-53)Online publication date: 18-Oct-2015
https://dl.acm.org/doi/10.1109/ICCD.2015.7357083
Widhalm DTauner SHorauer MSchumacher AHaggenmiller A(2015)A common platform for bridging pre- and post-silicon verification in mixed-signal designs2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings10.1109/I2MTC.2015.7151515(1584-1589)Online publication date: May-2015
https://doi.org/10.1109/I2MTC.2015.7151515
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