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A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation

Authors:

Fook-Luen Heng,

Zhan Chen,

Gustavo E. TellezAuthors Info & Claims

ISPD '97: Proceedings of the 1997 international symposium on Physical design

Pages 116 - 121

https://doi.org/10.1145/267665.267701

Published: 01 April 1997 Publication History

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Cited By

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Xu BBasaran BSu MPan DChu CBustany I(2018)Analog Placement Constraint Extraction and Exploration with the Application to Layout RetargetingProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3178245(98-105)Online publication date: 25-Mar-2018
https://dl.acm.org/doi/10.1145/3177540.3178245
Xu XPan D(2017)Toward Unidirectional Routing Closure in Advanced Technology NodesIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.10.210(2-12)Online publication date: 2017
https://doi.org/10.2197/ipsjtsldm.10.2
Salodkar NRajagopalan SBhattacharya SBatterywala S(2015)2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids2015 28th International Conference on VLSI Design10.1109/VLSID.2015.37(186-191)Online publication date: Jan-2015
https://doi.org/10.1109/VLSID.2015.37
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A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation

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Published In

ISPD '97: Proceedings of the 1997 international symposium on Physical design

April 1997

230 pages

ISBN:0897919270

DOI:10.1145/267665

Chairmen:
Andrew B. Kahng
Univ. of California, Los Angeles, and Cadence Design Systems, San Jose, CA
,
Majid Sarrafzadeh
Northwestern Univ., Evanston, IL

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1997

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ISPD97: 1997 International Symposium on Physical Design

April 14 - 16, 1997

California, Napa Valley, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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March 16 - 19, 2025

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Cited By

View all

Xu BBasaran BSu MPan DChu CBustany I(2018)Analog Placement Constraint Extraction and Exploration with the Application to Layout RetargetingProceedings of the 2018 International Symposium on Physical Design10.1145/3177540.3178245(98-105)Online publication date: 25-Mar-2018
https://dl.acm.org/doi/10.1145/3177540.3178245
Xu XPan D(2017)Toward Unidirectional Routing Closure in Advanced Technology NodesIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.10.210(2-12)Online publication date: 2017
https://doi.org/10.2197/ipsjtsldm.10.2
Salodkar NRajagopalan SBhattacharya SBatterywala S(2015)2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids2015 28th International Conference on VLSI Design10.1109/VLSID.2015.37(186-191)Online publication date: Jan-2015
https://doi.org/10.1109/VLSID.2015.37
Xu XCline BYeric GYu BPan D(2015)Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.239943934:5(699-712)Online publication date: May-2015
https://doi.org/10.1109/TCAD.2015.2399439
Xu XCline BYeric GYu BPan DSze CDavoodi A(2014)Self-aligned double patterning aware pin access and standard cell layout co-optimizationProceedings of the 2014 on International symposium on physical design10.1145/2560519.2560530(101-108)Online publication date: 30-Mar-2014
https://dl.acm.org/doi/10.1145/2560519.2560530
Bhattacharya SRajagopalan SBatterywala S(2014)Fixing Double Patterning violations with look-ahead2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2014.6742881(149-154)Online publication date: Jan-2014
https://doi.org/10.1109/ASPDAC.2014.6742881
Salodkar NRajagopalan SBhattacharya SBatterywala S(2013)Automatic design rule correction in presence of multiple grids and track patternsProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488766(1-6)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488766
Ghaida RAgarwal KNassif SYuan XLiebmann LGupta P(2013)Layout Decomposition and Legalization for Double-Patterning TechnologyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.223271032:2(202-215)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TCAD.2012.2232710
Ghaida RAgarwal KNassif SYuan XLiebmann LGupta PPhillips JHu AGraeb H(2011)A framework for double patterning-enabled designProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132329(14-20)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132329
Hsu CChang YNassif S(2011)Simultaneous Layout Migration and Decomposition for Double Patterning TechnologyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.207999030:2(284-294)Online publication date: 1-Feb-2011
https://dl.acm.org/doi/10.1109/TCAD.2010.2079990
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History-based VLSI legalization using network flow

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