research-article

EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs

Authors:

Meng-Yen Chuang,

Cheng-Hsuan Li,

Hsiang-Pang LiAuthors Info & Claims

DAC '14: Proceedings of the 51st Annual Design Automation Conference

Pages 1 - 6

https://doi.org/10.1145/2593069.2593130

Published: 01 June 2014 Publication History

Abstract

Low-density parity-check (LDPC) is widely accepted as the baseline error-correction codes offering strong error-correcting capability for future NAND flash-based SSDs. However, LDPC incurs read performance overhead because of its complex decoding procedure. To mitigate such overhead, we propose the error-correcting cache (EC-Cache) that exploits the "error locality" of NAND flash. Error locality means that the majority of errors in reads to the same NAND flash page appear in the same positions until the page is erased. By caching detected errors, EC-Cache can correct a significant portion of errors present in a requested flash page before the associated LDPC decoding process begins. EC-Cache can greatly speed up LDPC decoding because LDPC's latency is directly correlated to the number of errors present in the input data. Experimental results show that EC-Cache achieves up to 2.6× SSD read performance gain.

References

[1]

N. Agrawal, et al. Design tradeoffs for SSD performance. In USENIX ATC, 2008.

Digital Library

[2]

F. Arai, et al. Extended data retention process technology for highly reliable Flash EEPROMs of 106 to 107 W/E cycles. In IRPS, 1998.

[3]

J. S. Bucy, et al. DiskSim 4.0 (CMU-PDL-08-101). Technical report, Parallel Data Laboratory, 2008.

[4]

G. Dong, et al. On the use of soft-decision error-correction codes in NAND flash memory. IEEE Trans. Circuits Syst. Regul. Pap., 58(2):429--439, 2011.

[5]

G. Dong, et al. Reducing data transfer latency of NAND flash memory with soft-decision sensing. In ICC, 2012.

[6]

K.-C. Ho, et al. A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. In ISSCC, 2013.

[7]

X. Hu. LDPC codes for flash channel. In FMS '12, 2012.

[8]

J.-D. Lee, et al. Effects of floating-gate interference on NAND flash memory cell operation. IEEE Electron Device Lett., 23(5):264--266, 2002.

[9]

R.-S. Liu, et al. DuraCache: A durable SSD cache using MLC NAND flash. In DAC, 2013.

Digital Library

[10]

R. Micheloni, et al. Inside NAND Flash Memories. Springer, 2010.

[11]

N. Mielke, et al. Bit error rate in NAND flash memories. In IRPS, 2008.

[12]

D. Narayanan, et al. Write off-loading: practical power management for enterprise storage. In FAST, 2008.

Digital Library

[13]

R. M. Neal. Software for Low Density Parity Check Codes (Version of 2012-02-11), 2012.

[14]

T. Pritchett and M. Thottethodi. SieveStore: a highly-selective, ensemble-level disk cache for cost-performance. In ISCA, 2010.

Digital Library

[15]

S. Schechter, et al. Use ECP, not ECC, for hard failures in resistive memories. In ISCA, 2010.

Digital Library

[16]

S. Tanakamaru, et al. Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. In ASP-DAC, pages 83--84, 2013.

[17]

E. Yeo. An LDPC-enabled flash controller in 40 nm CMOS. In FMS, 2012.

[18]

K. Zhao, et al. LDPC-in-SSD: Making advanced error correction codes work effectively in solid state drives. In FAST, 2013.

Digital Library

[19]

W. Zhao, et al. Reducing latency overhead caused by using LDPC codes in NAND flash memory. EURASIP J. Adv. Sig. Proc., 2012:203, 2012.

Cited By

Wu WHsieh JKu H(2024)CDS: Coupled Data Storage to Enhance Read Performance of 3D TLC NAND Flash MemoryIEEE Transactions on Computers10.1109/TC.2023.333847473:3(694-707)Online publication date: Mar-2024
https://doi.org/10.1109/TC.2023.3338474
Chen JLi PXie P(2023)Flash-Based Solid-State Storage Reduces LDPC Read Retry SchemeProceedings of the 7th International Conference on Computer Science and Application Engineering10.1145/3627915.3628024(1-6)Online publication date: 17-Oct-2023
https://dl.acm.org/doi/10.1145/3627915.3628024
Du YHuang SZhou YLi Q(2023)Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error CharacteristicsACM Transactions on Design Automation of Electronic Systems10.1145/358507528:3(1-25)Online publication date: 18-Apr-2023
https://dl.acm.org/doi/10.1145/3585075
Show More Cited By

Index Terms

EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs
1. Hardware
  1. Hardware test
  2. Robustness
2. Information systems
  1. Information storage systems
    1. Storage management
      1. Hierarchical storage management

Recommendations

DuraCache: a durable SSD cache using MLC NAND flash
DAC '13: Proceedings of the 50th Annual Design Automation Conference

Adopting SSDs as caches for HDD arrays has gained popularity in datacenters because SSDs are superior in handling random reads that HDDs cannot efficiently deal with. Two types of flash memory cells are available for building SSD caches, single-level ...
Flash-Based Solid-State Storage Reduces LDPC Read Retry Scheme
CSAE '23: Proceedings of the 7th International Conference on Computer Science and Application Engineering

Flash memory, with its high performance and low power consumption, has been widely applied in various fields. The increasing storage density of flash memory has led to a gradual increase in Bit Error Rate (BER). Given the users' requirement for data ...
Combining Cache and Refresh to Optimize SSD Read Performance Scheme
Advanced Parallel Processing Technologies
Abstract
In the era of continuous advances in flash technology, the storage density of NAND flash memory is increasing, but the availability of data is declining. In order to improve data availability, low-density parity check codes (LDPC), which have been ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Other conferences

DAC '14: Proceedings of the 51st Annual Design Automation Conference

June 2014

1249 pages

ISBN:9781450327305

DOI:10.1145/2593069

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

In-Cooperation

EDAC: Electronic Design Automation Consortium
SIGBED: ACM Special Interest Group on Embedded Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2014

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

DAC '14

DAC '14: The 51st Annual Design Automation Conference 2014

June 1 - 5, 2014

CA, San Francisco, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

41
Total Citations
View Citations
285
Total Downloads

Downloads (Last 12 months)13
Downloads (Last 6 weeks)0

Reflects downloads up to 22 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Wu WHsieh JKu H(2024)CDS: Coupled Data Storage to Enhance Read Performance of 3D TLC NAND Flash MemoryIEEE Transactions on Computers10.1109/TC.2023.333847473:3(694-707)Online publication date: Mar-2024
https://doi.org/10.1109/TC.2023.3338474
Chen JLi PXie P(2023)Flash-Based Solid-State Storage Reduces LDPC Read Retry SchemeProceedings of the 7th International Conference on Computer Science and Application Engineering10.1145/3627915.3628024(1-6)Online publication date: 17-Oct-2023
https://dl.acm.org/doi/10.1145/3627915.3628024
Du YHuang SZhou YLi Q(2023)Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error CharacteristicsACM Transactions on Design Automation of Electronic Systems10.1145/358507528:3(1-25)Online publication date: 18-Apr-2023
https://dl.acm.org/doi/10.1145/3585075
Chen JHuang QZhai JShen ZHong JLanperne MPark JCerny TShahriar H(2023)CCFlash: A Correlation-Aware Compression Approach in Flash MemoryProceedings of the 38th ACM/SIGAPP Symposium on Applied Computing10.1145/3555776.3577673(80-87)Online publication date: 27-Mar-2023
https://dl.acm.org/doi/10.1145/3555776.3577673
Du YGao YHuang SLi Q(2023)LDPC Level Prediction Toward Read Performance of High-Density Flash MemoriesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.323884542:10(3264-3274)Online publication date: Oct-2023
https://doi.org/10.1109/TCAD.2023.3238845
Chen JLi PXie P(2023)Combining Cache and Refresh to Optimize SSD Read Performance SchemeAdvanced Parallel Processing Technologies10.1007/978-981-99-7872-4_7(113-129)Online publication date: 8-Nov-2023
https://doi.org/10.1007/978-981-99-7872-4_7
Jia MKong YZhan XZhang MWu FChen J(2022)Optimal Program-Read Schemes Toward Highly Reliable Open Block Operations in 3-D Charge-Trap NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313490041:11(4797-4807)Online publication date: Nov-2022
https://doi.org/10.1109/TCAD.2021.3134900
Zubair KGurumurthi SSridharan VAwad A(2021)Soteria: Towards Resilient Integrity-Protected and Encrypted Non-Volatile MemoriesMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480066(1214-1226)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480066
Zhang MWu FYu QLiu WCui LZhao YXie CDi Natale GFummi F(2020)BeLDPCProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408421(302-305)Online publication date: 9-Mar-2020
https://dl.acm.org/doi/10.5555/3408352.3408421
Zhang MWu FYu QLiu WCui LZhao YXie C(2020)BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116324(302-305)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116324
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents